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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-03 10:10:02 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-03 10:10:02 +0000 |
commit | fa487e83a83c260d6a50f3df00a0eb012553a912 (patch) | |
tree | f6ddd72df044eaa9cabbce37fd4b04f64b978139 /test/CodeGen/SystemZ/int-div-02.ll | |
parent | b81b477cd4392a51112c3af0659ea9fc176e74f1 (diff) | |
download | llvm-fa487e83a83c260d6a50f3df00a0eb012553a912.tar.gz llvm-fa487e83a83c260d6a50f3df00a0eb012553a912.tar.bz2 llvm-fa487e83a83c260d6a50f3df00a0eb012553a912.tar.xz |
[SystemZ] Fold more spills
Add a mapping from register-based <INSN>R instructions to the corresponding
memory-based <INSN>. Use it to cut down on the number of spill loads.
Some instructions extend their operands from smaller fields, so this
required a new TSFlags field to say how big the unextended operand is.
This optimisation doesn't trigger for C(G)R and CL(G)R because in practice
we always combine those instructions with a branch. Adding a test for every
other case probably seems excessive, but it did catch a missed optimisation
for DSGF (fixed in r185435).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/int-div-02.ll')
-rw-r--r-- | test/CodeGen/SystemZ/int-div-02.ll | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/int-div-02.ll b/test/CodeGen/SystemZ/int-div-02.ll index 7954384d29..b09172df9d 100644 --- a/test/CodeGen/SystemZ/int-div-02.ll +++ b/test/CodeGen/SystemZ/int-div-02.ll @@ -2,6 +2,8 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +declare i32 @foo() + ; Test register division. The result is in the second of the two registers. define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) { ; CHECK: f1: @@ -164,3 +166,46 @@ define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) { %rem = urem i32 %a, %b ret i32 %rem } + +; Check that divisions of spilled values can use DL rather than DLR. +define i32 @f13(i32 *%ptr0) { +; CHECK: f13: +; CHECK: brasl %r14, foo@PLT +; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15) +; CHECK: br %r14 + %ptr1 = getelementptr i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32 *%ptr0, i64 18 + + %val0 = load i32 *%ptr0 + %val1 = load i32 *%ptr1 + %val2 = load i32 *%ptr2 + %val3 = load i32 *%ptr3 + %val4 = load i32 *%ptr4 + %val5 = load i32 *%ptr5 + %val6 = load i32 *%ptr6 + %val7 = load i32 *%ptr7 + %val8 = load i32 *%ptr8 + %val9 = load i32 *%ptr9 + + %ret = call i32 @foo() + + %div0 = udiv i32 %ret, %val0 + %div1 = udiv i32 %div0, %val1 + %div2 = udiv i32 %div1, %val2 + %div3 = udiv i32 %div2, %val3 + %div4 = udiv i32 %div3, %val4 + %div5 = udiv i32 %div4, %val5 + %div6 = udiv i32 %div5, %val6 + %div7 = udiv i32 %div6, %val7 + %div8 = udiv i32 %div7, %val8 + %div9 = udiv i32 %div8, %val9 + + ret i32 %div9 +} |