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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-05-30 09:45:42 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-05-30 09:45:42 +0000
commit14a926f13b768ee3771bb944bbbb29529a40dbe1 (patch)
tree84c2dbb8c1cdb7bd841e955b875421c16a28e49b /test/CodeGen/SystemZ/int-move-08.ll
parentccb7bd9d84602c1fb5514dcee6de3420f175176a (diff)
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[SystemZ] Enable unaligned accesses
The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182920 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/int-move-08.ll')
-rw-r--r--test/CodeGen/SystemZ/int-move-08.ll50
1 files changed, 50 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/int-move-08.ll b/test/CodeGen/SystemZ/int-move-08.ll
index 5640fec329..e6022aa6ca 100644
--- a/test/CodeGen/SystemZ/int-move-08.ll
+++ b/test/CodeGen/SystemZ/int-move-08.ll
@@ -6,6 +6,10 @@
@gsrc32 = global i32 1
@gdst16 = global i16 2
@gdst32 = global i32 2
+@gsrc16u = global i16 1, align 1, section "foo"
+@gsrc32u = global i32 1, align 2, section "foo"
+@gdst16u = global i16 2, align 1, section "foo"
+@gdst32u = global i32 2, align 2, section "foo"
; Check sign-extending loads from i16.
define i32 @f1() {
@@ -47,3 +51,49 @@ define void @f4() {
store i32 %val, i32 *@gdst32
ret void
}
+
+; Repeat f1 with an unaligned variable.
+define i32 @f5() {
+; CHECK: f5:
+; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
+; CHECK: lh %r2, 0([[REG]])
+; CHECK: br %r14
+ %val = load i16 *@gsrc16u, align 1
+ %ext = sext i16 %val to i32
+ ret i32 %ext
+}
+
+; Repeat f2 with an unaligned variable.
+define i32 @f6() {
+; CHECK: f6:
+; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
+; CHECK: llh %r2, 0([[REG]])
+; CHECK: br %r14
+ %val = load i16 *@gsrc16u, align 1
+ %ext = zext i16 %val to i32
+ ret i32 %ext
+}
+
+; Repeat f3 with an unaligned variable.
+define void @f7(i32 %val) {
+; CHECK: f7:
+; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
+; CHECK: sth %r2, 0([[REG]])
+; CHECK: br %r14
+ %half = trunc i32 %val to i16
+ store i16 %half, i16 *@gdst16u, align 1
+ ret void
+}
+
+; Repeat f4 with unaligned variables.
+define void @f8() {
+; CHECK: f8:
+; CHECK: larl [[REG:%r[0-5]]], gsrc32u
+; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
+; CHECK: larl [[REG:%r[0-5]]], gdst32u
+; CHECK: st [[VAL]], 0([[REG]])
+; CHECK: br %r14
+ %val = load i32 *@gsrc32u, align 2
+ store i32 %val, i32 *@gdst32u, align 2
+ ret void
+}