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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-12-20 11:49:48 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-12-20 11:49:48 +0000 |
| commit | 1fd4e558289771a2d5b70f0da8155e0ba2721a49 (patch) | |
| tree | 89d130f91a37796395c0291c1c754e7fd4adb4f9 /test/CodeGen/SystemZ | |
| parent | 78a613731e39778fd6e4518b7d4738bd0c0de291 (diff) | |
| download | llvm-1fd4e558289771a2d5b70f0da8155e0ba2721a49.tar.gz llvm-1fd4e558289771a2d5b70f0da8155e0ba2721a49.tar.bz2 llvm-1fd4e558289771a2d5b70f0da8155e0ba2721a49.tar.xz | |
[SystemZ] Extend RISBG optimization
The handling of ANY_EXTEND and ZERO_EXTEND was too strict. In this context
we can treat ZERO_EXTEND in much the same way as an AND and then also handle
outermost ZERO_EXTENDs.
I couldn't find a test that benefited from the ANY_EXTEND change, but it's
more obvious to write it this way once SIGN_EXTEND and ZERO_EXTEND are
handled differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197802 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ')
| -rw-r--r-- | test/CodeGen/SystemZ/risbg-01.ll | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll index a4d11fdae5..e303067e53 100644 --- a/test/CodeGen/SystemZ/risbg-01.ll +++ b/test/CodeGen/SystemZ/risbg-01.ll @@ -457,11 +457,22 @@ define i64 @f40(i64 %foo, i64 *%dest) { ret i64 %and } +; Check a case where the result is zero-extended. +define i64 @f41(i32 %a) { +; CHECK-LABEL: f41 +; CHECK: risbg %r2, %r2, 36, 191, 62 +; CHECK: br %r14 + %shl = shl i32 %a, 2 + %shr = lshr i32 %shl, 4 + %ext = zext i32 %shr to i64 + ret i64 %ext +} + ; In this case the sign extension is converted to a pair of 32-bit shifts, ; which is then extended to 64 bits. We previously used the wrong bit size ; when testing whether the shifted-in bits of the shift right were significant. -define i64 @f41(i1 %x) { -; CHECK-LABEL: f41: +define i64 @f42(i1 %x) { +; CHECK-LABEL: f42: ; CHECK: sll %r2, 31 ; CHECK: sra %r2, 31 ; CHECK: llgcr %r2, %r2 |