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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-12-10 10:49:34 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-12-10 10:49:34 +0000 |
commit | aedb288d864bf20a708cca580fa87ac848389f79 (patch) | |
tree | 433a286e31fa441c4784a9d1b95ce1eb49e97032 /test/CodeGen/SystemZ | |
parent | 086791eca2260c03c7bbdd37a53626d16656f0ca (diff) | |
download | llvm-aedb288d864bf20a708cca580fa87ac848389f79.tar.gz llvm-aedb288d864bf20a708cca580fa87ac848389f79.tar.bz2 llvm-aedb288d864bf20a708cca580fa87ac848389f79.tar.xz |
Add TargetLowering::prepareVolatileOrAtomicLoad
One unusual feature of the z architecture is that the result of a
previous load can be reused indefinitely for subsequent loads, even if
a cache-coherent store to that location is performed by another CPU.
A special serializing instruction must be used if you want to force
a load to be reattempted.
Since volatile loads are not supposed to be omitted in this way,
we should insert a serializing instruction before each such load.
The same goes for atomic loads.
The patch implements this at the IR->DAG boundary, in a similar way
to atomic fences. It is a no-op for targets other than SystemZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196906 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ')
-rw-r--r-- | test/CodeGen/SystemZ/atomic-load-01.ll | 5 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomic-load-02.ll | 5 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomic-load-03.ll | 8 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomic-load-04.ll | 8 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomic-store-01.ll | 5 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomic-store-02.ll | 5 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomic-store-03.ll | 8 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomic-store-04.ll | 8 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/cond-store-01.ll | 7 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/cond-store-02.ll | 7 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/cond-store-03.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/cond-store-04.ll | 4 |
12 files changed, 28 insertions, 46 deletions
diff --git a/test/CodeGen/SystemZ/atomic-load-01.ll b/test/CodeGen/SystemZ/atomic-load-01.ll index a5bc8833e7..f3acd605b0 100644 --- a/test/CodeGen/SystemZ/atomic-load-01.ll +++ b/test/CodeGen/SystemZ/atomic-load-01.ll @@ -2,11 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that loads are handled. -; The CS-based sequence is probably far too conservative. define i8 @f1(i8 *%src) { ; CHECK-LABEL: f1: -; CHECK: cs +; CHECK: bcr 1{{[45]}}, %r0 +; CHECK: lb %r2, 0(%r2) ; CHECK: br %r14 %val = load atomic i8 *%src seq_cst, align 1 ret i8 %val diff --git a/test/CodeGen/SystemZ/atomic-load-02.ll b/test/CodeGen/SystemZ/atomic-load-02.ll index 2c9bbdb488..d9bec60f4c 100644 --- a/test/CodeGen/SystemZ/atomic-load-02.ll +++ b/test/CodeGen/SystemZ/atomic-load-02.ll @@ -2,11 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that loads are handled. -; The CS-based sequence is probably far too conservative. define i16 @f1(i16 *%src) { ; CHECK-LABEL: f1: -; CHECK: cs +; CHECK: bcr 1{{[45]}}, %r0 +; CHECK: lh %r2, 0(%r2) ; CHECK: br %r14 %val = load atomic i16 *%src seq_cst, align 2 ret i16 %val diff --git a/test/CodeGen/SystemZ/atomic-load-03.ll b/test/CodeGen/SystemZ/atomic-load-03.ll index 1fb41f5e39..7e5eb9249a 100644 --- a/test/CodeGen/SystemZ/atomic-load-03.ll +++ b/test/CodeGen/SystemZ/atomic-load-03.ll @@ -2,12 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that loads are handled. -; Using CS is probably too conservative. -define i32 @f1(i32 %dummy, i32 *%src) { +define i32 @f1(i32 *%src) { ; CHECK-LABEL: f1: -; CHECK: lhi %r2, 0 -; CHECK: cs %r2, %r2, 0(%r3) +; CHECK: bcr 1{{[45]}}, %r0 +; CHECK: l %r2, 0(%r2) ; CHECK: br %r14 %val = load atomic i32 *%src seq_cst, align 4 ret i32 %val diff --git a/test/CodeGen/SystemZ/atomic-load-04.ll b/test/CodeGen/SystemZ/atomic-load-04.ll index 92cac406e2..c7a9a98a42 100644 --- a/test/CodeGen/SystemZ/atomic-load-04.ll +++ b/test/CodeGen/SystemZ/atomic-load-04.ll @@ -2,12 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that loads are handled. -; Using CSG is probably too conservative. -define i64 @f1(i64 %dummy, i64 *%src) { +define i64 @f1(i64 *%src) { ; CHECK-LABEL: f1: -; CHECK: lghi %r2, 0 -; CHECK: csg %r2, %r2, 0(%r3) +; CHECK: bcr 1{{[45]}}, %r0 +; CHECK: lg %r2, 0(%r2) ; CHECK: br %r14 %val = load atomic i64 *%src seq_cst, align 8 ret i64 %val diff --git a/test/CodeGen/SystemZ/atomic-store-01.ll b/test/CodeGen/SystemZ/atomic-store-01.ll index 53ed24f623..952e1a9121 100644 --- a/test/CodeGen/SystemZ/atomic-store-01.ll +++ b/test/CodeGen/SystemZ/atomic-store-01.ll @@ -2,11 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that stores are handled. -; The CS-based sequence is probably far too conservative. define void @f1(i8 %val, i8 *%src) { ; CHECK-LABEL: f1: -; CHECK: cs +; CHECK: stc %r2, 0(%r3) +; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: br %r14 store atomic i8 %val, i8 *%src seq_cst, align 1 ret void diff --git a/test/CodeGen/SystemZ/atomic-store-02.ll b/test/CodeGen/SystemZ/atomic-store-02.ll index 42d6695b51..c9576e5565 100644 --- a/test/CodeGen/SystemZ/atomic-store-02.ll +++ b/test/CodeGen/SystemZ/atomic-store-02.ll @@ -2,11 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that stores are handled. -; The CS-based sequence is probably far too conservative. define void @f1(i16 %val, i16 *%src) { ; CHECK-LABEL: f1: -; CHECK: cs +; CHECK: sth %r2, 0(%r3) +; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: br %r14 store atomic i16 %val, i16 *%src seq_cst, align 2 ret void diff --git a/test/CodeGen/SystemZ/atomic-store-03.ll b/test/CodeGen/SystemZ/atomic-store-03.ll index 846c86fd36..459cb6a94e 100644 --- a/test/CodeGen/SystemZ/atomic-store-03.ll +++ b/test/CodeGen/SystemZ/atomic-store-03.ll @@ -2,14 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that stores are handled. -; Using CS is probably too conservative. define void @f1(i32 %val, i32 *%src) { ; CHECK-LABEL: f1: -; CHECK: l %r0, 0(%r3) -; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: cs %r0, %r2, 0(%r3) -; CHECK: jl [[LABEL]] +; CHECK: st %r2, 0(%r3) +; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: br %r14 store atomic i32 %val, i32 *%src seq_cst, align 4 ret void diff --git a/test/CodeGen/SystemZ/atomic-store-04.ll b/test/CodeGen/SystemZ/atomic-store-04.ll index 24615b1156..7f2406eb54 100644 --- a/test/CodeGen/SystemZ/atomic-store-04.ll +++ b/test/CodeGen/SystemZ/atomic-store-04.ll @@ -2,14 +2,10 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; This is just a placeholder to make sure that stores are handled. -; Using CS is probably too conservative. define void @f1(i64 %val, i64 *%src) { ; CHECK-LABEL: f1: -; CHECK: lg %r0, 0(%r3) -; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: csg %r0, %r2, 0(%r3) -; CHECK: jl [[LABEL]] +; CHECK: stg %r2, 0(%r3) +; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: br %r14 store atomic i64 %val, i64 *%src seq_cst, align 8 ret void diff --git a/test/CodeGen/SystemZ/cond-store-01.ll b/test/CodeGen/SystemZ/cond-store-01.ll index d55ea2133e..62e9796fa2 100644 --- a/test/CodeGen/SystemZ/cond-store-01.ll +++ b/test/CodeGen/SystemZ/cond-store-01.ll @@ -347,11 +347,10 @@ define void @f19(i8 *%ptr, i8 %alt, i32 %limit) { define void @f20(i8 *%ptr, i8 %alt, i32 %limit) { ; FIXME: should use a normal load instead of CS. ; CHECK-LABEL: f20: -; CHECK: cs {{%r[0-9]+}}, -; CHECK: jl +; CHECK: lb {{%r[0-9]+}}, 0(%r2) ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]] ; CHECK: [[LABEL]]: -; CHECK: stc {{%r[0-9]+}}, +; CHECK: stc {{%r[0-9]+}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load atomic i8 *%ptr unordered, align 1 @@ -367,7 +366,7 @@ define void @f21(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK: jhe [[LABEL:[^ ]*]] ; CHECK: lb %r3, 0(%r2) ; CHECK: [[LABEL]]: -; CHECK: cs {{%r[0-9]+}}, +; CHECK: stc %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 *%ptr diff --git a/test/CodeGen/SystemZ/cond-store-02.ll b/test/CodeGen/SystemZ/cond-store-02.ll index 91bc4860b3..4fbcdaba51 100644 --- a/test/CodeGen/SystemZ/cond-store-02.ll +++ b/test/CodeGen/SystemZ/cond-store-02.ll @@ -347,11 +347,10 @@ define void @f19(i16 *%ptr, i16 %alt, i32 %limit) { define void @f20(i16 *%ptr, i16 %alt, i32 %limit) { ; FIXME: should use a normal load instead of CS. ; CHECK-LABEL: f20: -; CHECK: cs {{%r[0-9]+}}, -; CHECK: jl +; CHECK: lh {{%r[0-9]+}}, 0(%r2) ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]] ; CHECK: [[LABEL]]: -; CHECK: sth {{%r[0-9]+}}, +; CHECK: sth {{%r[0-9]+}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load atomic i16 *%ptr unordered, align 2 @@ -367,7 +366,7 @@ define void @f21(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK: jhe [[LABEL:[^ ]*]] ; CHECK: lh %r3, 0(%r2) ; CHECK: [[LABEL]]: -; CHECK: cs {{%r[0-9]+}}, +; CHECK: sth %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 *%ptr diff --git a/test/CodeGen/SystemZ/cond-store-03.ll b/test/CodeGen/SystemZ/cond-store-03.ll index d4fd48d613..4b22555d0d 100644 --- a/test/CodeGen/SystemZ/cond-store-03.ll +++ b/test/CodeGen/SystemZ/cond-store-03.ll @@ -272,7 +272,7 @@ define void @f15(i32 *%ptr, i32 %alt, i32 %limit) { define void @f16(i32 *%ptr, i32 %alt, i32 %limit) { ; FIXME: should use a normal load instead of CS. ; CHECK-LABEL: f16: -; CHECK: cs {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2) +; CHECK: l {{%r[0-5]}}, 0(%r2) ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]] ; CHECK: [[LABEL]]: ; CHECK: st {{%r[0-5]}}, 0(%r2) @@ -291,7 +291,7 @@ define void @f17(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: jhe [[LABEL:[^ ]*]] ; CHECK: l %r3, 0(%r2) ; CHECK: [[LABEL]]: -; CHECK: cs {{%r[0-5]}}, %r3, 0(%r2) +; CHECK: st %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i32 *%ptr diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll index fc565c432f..346b51a17d 100644 --- a/test/CodeGen/SystemZ/cond-store-04.ll +++ b/test/CodeGen/SystemZ/cond-store-04.ll @@ -164,7 +164,7 @@ define void @f9(i64 *%ptr, i64 %alt, i32 %limit) { define void @f10(i64 *%ptr, i64 %alt, i32 %limit) { ; FIXME: should use a normal load instead of CSG. ; CHECK-LABEL: f10: -; CHECK: csg {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2) +; CHECK: lg {{%r[0-5]}}, 0(%r2) ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]] ; CHECK: [[LABEL]]: ; CHECK: stg {{%r[0-5]}}, 0(%r2) @@ -183,7 +183,7 @@ define void @f11(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: jhe [[LABEL:[^ ]*]] ; CHECK: lg %r3, 0(%r2) ; CHECK: [[LABEL]]: -; CHECK: csg {{%r[0-5]}}, %r3, 0(%r2) +; CHECK: stg %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i64 *%ptr |