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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-19 16:21:55 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-19 16:21:55 +0000 |
commit | db92fb07169af6941dfe47439f9849d370f0eb0b (patch) | |
tree | 0e2cc8604ad34832f39bdb4c980252f34cfa09f0 /test/CodeGen/SystemZ | |
parent | cae5d5ea658e05091e66b742b5834f1896ff2f5d (diff) | |
download | llvm-db92fb07169af6941dfe47439f9849d370f0eb0b.tar.gz llvm-db92fb07169af6941dfe47439f9849d370f0eb0b.tar.bz2 llvm-db92fb07169af6941dfe47439f9849d370f0eb0b.tar.xz |
[SystemZ] Add NRK, ORK and XRK
The atomic tests assume the two-operand forms, so I've restricted them to z10.
Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried). Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186683 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ')
-rw-r--r-- | test/CodeGen/SystemZ/and-01.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/and-07.ll | 21 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomicrmw-and-03.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomicrmw-nand-03.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomicrmw-or-03.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/atomicrmw-xor-03.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/or-01.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/or-07.ll | 21 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/xor-01.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/SystemZ/xor-07.ll | 21 |
10 files changed, 73 insertions, 7 deletions
diff --git a/test/CodeGen/SystemZ/and-01.ll b/test/CodeGen/SystemZ/and-01.ll index f89314809f..3b230ba108 100644 --- a/test/CodeGen/SystemZ/and-01.ll +++ b/test/CodeGen/SystemZ/and-01.ll @@ -1,6 +1,7 @@ ; Test 32-bit ANDs in which the second operand is variable. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s declare i32 @foo() diff --git a/test/CodeGen/SystemZ/and-07.ll b/test/CodeGen/SystemZ/and-07.ll new file mode 100644 index 0000000000..2bdf97d470 --- /dev/null +++ b/test/CodeGen/SystemZ/and-07.ll @@ -0,0 +1,21 @@ +; Test the three-operand forms of AND. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s + +; Check NRK. +define i32 @f1(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: f1: +; CHECK: nrk %r2, %r3, %r4 +; CHECK: br %r14 + %and = and i32 %b, %c + ret i32 %and +} + +; Check that we can still use NR in obvious cases. +define i32 @f2(i32 %a, i32 %b) { +; CHECK-LABEL: f2: +; CHECK: nr %r2, %r3 +; CHECK: br %r14 + %and = and i32 %a, %b + ret i32 %and +} diff --git a/test/CodeGen/SystemZ/atomicrmw-and-03.ll b/test/CodeGen/SystemZ/atomicrmw-and-03.ll index dd02828ad8..6c7ba23e1b 100644 --- a/test/CodeGen/SystemZ/atomicrmw-and-03.ll +++ b/test/CodeGen/SystemZ/atomicrmw-and-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic ANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Check ANDs of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll index be306a29e3..c511bd608f 100644 --- a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll +++ b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic NANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Check NANDs of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { diff --git a/test/CodeGen/SystemZ/atomicrmw-or-03.ll b/test/CodeGen/SystemZ/atomicrmw-or-03.ll index 6386847e53..692b11c4cf 100644 --- a/test/CodeGen/SystemZ/atomicrmw-or-03.ll +++ b/test/CodeGen/SystemZ/atomicrmw-or-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic ORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Check ORs of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll index 292de3642b..05754e7a0e 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll @@ -1,6 +1,6 @@ ; Test 32-bit atomic XORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Check XORs of a variable. define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { diff --git a/test/CodeGen/SystemZ/or-01.ll b/test/CodeGen/SystemZ/or-01.ll index ee0a39228d..23946d3206 100644 --- a/test/CodeGen/SystemZ/or-01.ll +++ b/test/CodeGen/SystemZ/or-01.ll @@ -1,6 +1,7 @@ ; Test 32-bit ORs in which the second operand is variable. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s declare i32 @foo() diff --git a/test/CodeGen/SystemZ/or-07.ll b/test/CodeGen/SystemZ/or-07.ll new file mode 100644 index 0000000000..f6848a1659 --- /dev/null +++ b/test/CodeGen/SystemZ/or-07.ll @@ -0,0 +1,21 @@ +; Test the three-operand forms of OR. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s + +; Check XRK. +define i32 @f1(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: f1: +; CHECK: ork %r2, %r3, %r4 +; CHECK: br %r14 + %or = or i32 %b, %c + ret i32 %or +} + +; Check that we can still use OR in obvious cases. +define i32 @f2(i32 %a, i32 %b) { +; CHECK-LABEL: f2: +; CHECK: or %r2, %r3 +; CHECK: br %r14 + %or = or i32 %a, %b + ret i32 %or +} diff --git a/test/CodeGen/SystemZ/xor-01.ll b/test/CodeGen/SystemZ/xor-01.ll index f9ba2eb65e..185d6bb0a7 100644 --- a/test/CodeGen/SystemZ/xor-01.ll +++ b/test/CodeGen/SystemZ/xor-01.ll @@ -1,6 +1,7 @@ ; Test 32-bit XORs in which the second operand is variable. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s declare i32 @foo() diff --git a/test/CodeGen/SystemZ/xor-07.ll b/test/CodeGen/SystemZ/xor-07.ll new file mode 100644 index 0000000000..22deef64ce --- /dev/null +++ b/test/CodeGen/SystemZ/xor-07.ll @@ -0,0 +1,21 @@ +; Test the three-operand forms of XOR. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s + +; Check XRK. +define i32 @f1(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: f1: +; CHECK: xrk %r2, %r3, %r4 +; CHECK: br %r14 + %xor = xor i32 %b, %c + ret i32 %xor +} + +; Check that we can still use XR in obvious cases. +define i32 @f2(i32 %a, i32 %b) { +; CHECK-LABEL: f2: +; CHECK: xr %r2, %r3 +; CHECK: br %r14 + %xor = xor i32 %a, %b + ret i32 %xor +} |