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| author | Bob Wilson <bob.wilson@apple.com> | 2010-02-13 00:31:44 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-02-13 00:31:44 +0000 |
| commit | bf9b221c006a99d6f117c1048412859d5637bcde (patch) | |
| tree | cd3c5edb01642b2a7cf6f59ed13a8b28e1489359 /test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll | |
| parent | 39125d8ef94cbadccd7339d3344e114dedaab12c (diff) | |
| download | llvm-bf9b221c006a99d6f117c1048412859d5637bcde.tar.gz llvm-bf9b221c006a99d6f117c1048412859d5637bcde.tar.bz2 llvm-bf9b221c006a99d6f117c1048412859d5637bcde.tar.xz | |
Besides removing phi cycles that reduce to a single value, also remove dead
phi cycles. Adjust a few tests to keep dead instructions from being optimized
away. This (together with my previous change for phi cycles) fixes Apple
radar 7627077.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96057 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll b/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll index 997257885e..0f23ee7568 100644 --- a/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll +++ b/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll @@ -29,6 +29,44 @@ return: ; preds = %bb, %entry ret i32 undef } +define arm_apcscc i32 @test_dead_cycle(i32 %n) nounwind { +; CHECK: test_dead_cycle: +; CHECK: blx +; CHECK-NOT: mov +; CHECK: blx +entry: + %0 = icmp eq i32 %n, 1 ; <i1> [#uses=1] + br i1 %0, label %return, label %bb.nph + +bb.nph: ; preds = %entry + %tmp = add i32 %n, -1 ; <i32> [#uses=2] + br label %bb + +bb: ; preds = %bb.nph, %bb2 + %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb2 ] ; <i32> [#uses=2] + %u.17 = phi i64 [ undef, %bb.nph ], [ %u.0, %bb2 ] ; <i64> [#uses=2] + %tmp9 = sub i32 %tmp, %indvar ; <i32> [#uses=1] + %1 = icmp sgt i32 %tmp9, 1 ; <i1> [#uses=1] + br i1 %1, label %bb1, label %bb2 + +bb1: ; preds = %bb + %2 = tail call arm_apcscc i32 @f() nounwind ; <i32> [#uses=1] + %tmp6 = zext i32 %2 to i64 ; <i64> [#uses=1] + %mask = and i64 %u.17, -4294967296 ; <i64> [#uses=1] + %ins = or i64 %tmp6, %mask ; <i64> [#uses=1] + tail call arm_apcscc void @g(i64 %ins) nounwind + br label %bb2 + +bb2: ; preds = %bb1, %bb + %u.0 = phi i64 [ %ins, %bb1 ], [ %u.17, %bb ] ; <i64> [#uses=2] + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %tmp ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb2, %entry + ret i32 undef +} + declare arm_apcscc i32 @f() declare arm_apcscc void @g(i64) |