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| author | Bob Wilson <bob.wilson@apple.com> | 2010-02-12 01:30:21 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-02-12 01:30:21 +0000 |
| commit | fe61fb1e1082c81653ed78efd6d471592a2e57ad (patch) | |
| tree | df0bb339b5cb79a8d22e66430b920e47fae100a5 /test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll | |
| parent | ccfa1db5380fd3089fc68f3ed9ccfe6a41d7a309 (diff) | |
| download | llvm-fe61fb1e1082c81653ed78efd6d471592a2e57ad.tar.gz llvm-fe61fb1e1082c81653ed78efd6d471592a2e57ad.tar.bz2 llvm-fe61fb1e1082c81653ed78efd6d471592a2e57ad.tar.xz | |
Add a new pass on machine instructions to optimize away PHI cycles that
reduce down to a single value. InstCombine already does this transformation
but DAG legalization may introduce new opportunities. This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized. I measured the compile time
impact of this (running llc on 176.gcc) and it was not significant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95951 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll b/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll new file mode 100644 index 0000000000..997257885e --- /dev/null +++ b/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" + +define arm_apcscc i32 @test(i32 %n) nounwind { +; CHECK: test: +; CHECK-NOT: mov +; CHECK: return +entry: + %0 = icmp eq i32 %n, 1 ; <i1> [#uses=1] + br i1 %0, label %return, label %bb.nph + +bb.nph: ; preds = %entry + %tmp = add i32 %n, -1 ; <i32> [#uses=1] + br label %bb + +bb: ; preds = %bb.nph, %bb + %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=1] + %u.05 = phi i64 [ undef, %bb.nph ], [ %ins, %bb ] ; <i64> [#uses=1] + %1 = tail call arm_apcscc i32 @f() nounwind ; <i32> [#uses=1] + %tmp4 = zext i32 %1 to i64 ; <i64> [#uses=1] + %mask = and i64 %u.05, -4294967296 ; <i64> [#uses=1] + %ins = or i64 %tmp4, %mask ; <i64> [#uses=2] + tail call arm_apcscc void @g(i64 %ins) nounwind + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %tmp ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret i32 undef +} + +declare arm_apcscc i32 @f() + +declare arm_apcscc void @g(i64) |