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| author | Evan Cheng <evan.cheng@apple.com> | 2010-11-17 20:13:28 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-11-17 20:13:28 +0000 |
| commit | c4af4638dfdab0dc3b6257276cfad2ee45053060 (patch) | |
| tree | c09b56536b88953a85defe07d095b13cfa625b03 /test/CodeGen/Thumb2/thumb2-select_xform.ll | |
| parent | f2dc4aa562e2478a73fe5aeeeec16b1e496a0642 (diff) | |
| download | llvm-c4af4638dfdab0dc3b6257276cfad2ee45053060.tar.gz llvm-c4af4638dfdab0dc3b6257276cfad2ee45053060.tar.bz2 llvm-c4af4638dfdab0dc3b6257276cfad2ee45053060.tar.xz | |
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/thumb2-select_xform.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/thumb2-select_xform.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/Thumb2/thumb2-select_xform.ll b/test/CodeGen/Thumb2/thumb2-select_xform.ll index 56cb1f6fb4..ceefabbbfa 100644 --- a/test/CodeGen/Thumb2/thumb2-select_xform.ll +++ b/test/CodeGen/Thumb2/thumb2-select_xform.ll @@ -2,8 +2,8 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK: t1 -; CHECK: sub.w r0, r1, #-2147483648 -; CHECK: subs r0, #1 +; CHECK: mvn r0, #-2147483648 +; CHECK: add r0, r1 ; CHECK: cmp r2, #10 ; CHECK: it gt ; CHECK: movgt r0, r1 |