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| author | Andrew Trick <atrick@apple.com> | 2011-04-23 03:55:32 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-04-23 03:55:32 +0000 |
| commit | 1c3af779fc6b184204efd7e98dc16e475c251e7f (patch) | |
| tree | d9ca1d20f7c3930939492236cac207ad0c5e0fc9 /test/CodeGen/Thumb2/thumb2-sub3.ll | |
| parent | 1611bcd6acd685052eae9927f3ffbbfc917f1233 (diff) | |
| download | llvm-1c3af779fc6b184204efd7e98dc16e475c251e7f.tar.gz llvm-1c3af779fc6b184204efd7e98dc16e475c251e7f.tar.bz2 llvm-1c3af779fc6b184204efd7e98dc16e475c251e7f.tar.xz | |
Thumb2 and ARM add/subtract with carry fixes.
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.
Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.
Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2/thumb2-sub3.ll')
| -rw-r--r-- | test/CodeGen/Thumb2/thumb2-sub3.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/Thumb2/thumb2-sub3.ll b/test/CodeGen/Thumb2/thumb2-sub3.ll index 855ad06a63..1dbda57f23 100644 --- a/test/CodeGen/Thumb2/thumb2-sub3.ll +++ b/test/CodeGen/Thumb2/thumb2-sub3.ll @@ -4,7 +4,7 @@ define i64 @f1(i64 %a) { ; CHECK: f1 ; CHECK: subs r0, #171 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 171 ret i64 %tmp } @@ -13,7 +13,7 @@ define i64 @f1(i64 %a) { define i64 @f2(i64 %a) { ; CHECK: f2 ; CHECK: subs.w r0, r0, #1179666 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 1179666 ret i64 %tmp } @@ -22,7 +22,7 @@ define i64 @f2(i64 %a) { define i64 @f3(i64 %a) { ; CHECK: f3 ; CHECK: subs.w r0, r0, #872428544 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 872428544 ret i64 %tmp } @@ -31,7 +31,7 @@ define i64 @f3(i64 %a) { define i64 @f4(i64 %a) { ; CHECK: f4 ; CHECK: subs.w r0, r0, #1448498774 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 1448498774 ret i64 %tmp } @@ -40,7 +40,7 @@ define i64 @f4(i64 %a) { define i64 @f5(i64 %a) { ; CHECK: f5 ; CHECK: subs.w r0, r0, #66846720 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 66846720 ret i64 %tmp } |