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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-19 00:55:07 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-19 00:55:07 +0000 |
| commit | 11e8b74a7ae9ecd59b64180a59143e39bc3b9514 (patch) | |
| tree | 23c9e8ebbd1f15df2c90829c4bf6669a0aa0940b /test/CodeGen/X86/2008-10-27-CoalescerBug.ll | |
| parent | b5a2d3f8e3b40c3076d03c5db7c4f0387e58b53b (diff) | |
| download | llvm-11e8b74a7ae9ecd59b64180a59143e39bc3b9514.tar.gz llvm-11e8b74a7ae9ecd59b64180a59143e39bc3b9514.tar.bz2 llvm-11e8b74a7ae9ecd59b64180a59143e39bc3b9514.tar.xz | |
- Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/2008-10-27-CoalescerBug.ll')
| -rw-r--r-- | test/CodeGen/X86/2008-10-27-CoalescerBug.ll | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/test/CodeGen/X86/2008-10-27-CoalescerBug.ll b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll index afeb358da5..9d144a4be0 100644 --- a/test/CodeGen/X86/2008-10-27-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll @@ -1,6 +1,9 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& not grep {Number of register spills} +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -stats |& FileCheck %s +; Now this test spills one register. But a reload in the loop is cheaper than +; the divsd so it's a win. define fastcc void @fourn(double* %data, i32 %isign) nounwind { +; CHECK: fourn entry: br label %bb @@ -11,6 +14,11 @@ bb: ; preds = %bb, %entry %1 = icmp sgt i32 %0, 2 ; <i1> [#uses=1] br i1 %1, label %bb30.loopexit, label %bb +; CHECK: %bb30.loopexit +; CHECK: divsd %xmm0 +; CHECK: movsd %xmm0, 16(%esp) +; CHECK: .align +; CHECK-NEXT: %bb3 bb3: ; preds = %bb30.loopexit, %bb25, %bb3 %2 = load i32* null, align 4 ; <i32> [#uses=1] %3 = mul i32 %2, 0 ; <i32> [#uses=1] |