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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-09 19:27:06 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-09 19:27:06 +0000 |
| commit | 5d96e5a1ccbdc4d64db4e15418392bb7c61e4d6f (patch) | |
| tree | b48fc27fb9e25bb4271021437c25a3d3f5281d1f /test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll | |
| parent | dda386c44d994d59593f5281155378fbe865d364 (diff) | |
| download | llvm-5d96e5a1ccbdc4d64db4e15418392bb7c61e4d6f.tar.gz llvm-5d96e5a1ccbdc4d64db4e15418392bb7c61e4d6f.tar.bz2 llvm-5d96e5a1ccbdc4d64db4e15418392bb7c61e4d6f.tar.xz | |
Make physreg coalescing independent on the number of uses of the virtual register.
The damage done by physreg coalescing only depends on the number of instructions
the extended physreg live range covers. This fixes PR9438.
The heuristic is still luck-based, and physreg coalescing really should be
disabled completely. We need a register allocator with better hinting support
before that is possible.
Convert a test to FileCheck and force spilling by inserting an extra call. The
previous spilling behavior was dependent on misguided physreg coalescing
decisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127351 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll')
| -rw-r--r-- | test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll b/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll new file mode 100644 index 0000000000..e48edf7e30 --- /dev/null +++ b/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll @@ -0,0 +1,22 @@ +; RUN: llc -mcpu=yonah < %s +; PR9438 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-unknown-freebsd9.0" + +; The 'call fastcc' ties down %ebx, %ecx, and %edx. +; A MUL8r ties down %al, leaving no GR32_ABCD registers available. +; The coalescer can easily overallocate physical registers, +; and register allocation fails. + +declare fastcc i8* @save_string(i8* %d, i8* nocapture %s) nounwind + +define i32 @cvtchar(i8* nocapture %sp) nounwind { + %temp.i = alloca [2 x i8], align 1 + %tmp1 = load i8* %sp, align 1 + %div = udiv i8 %tmp1, 10 + %rem = urem i8 %div, 10 + %arrayidx.i = getelementptr inbounds [2 x i8]* %temp.i, i32 0, i32 0 + store i8 %rem, i8* %arrayidx.i, align 1 + %call.i = call fastcc i8* @save_string(i8* %sp, i8* %arrayidx.i) nounwind + ret i32 undef +} |