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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2013-12-27 20:20:28 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2013-12-27 20:20:28 +0000 |
| commit | b2f47c6a3455a9d265e21c8ab1ca81657ff577a0 (patch) | |
| tree | cfaadbd40840df2293deec78b068ce832fafb91f /test/CodeGen/X86/2011-12-28-vselecti8.ll | |
| parent | bd75475bfcbf81c0f6e3a67511c16704c7da8b7a (diff) | |
| download | llvm-b2f47c6a3455a9d265e21c8ab1ca81657ff577a0.tar.gz llvm-b2f47c6a3455a9d265e21c8ab1ca81657ff577a0.tar.bz2 llvm-b2f47c6a3455a9d265e21c8ab1ca81657ff577a0.tar.xz | |
Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR of
ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR.
For example, given the following sequence of dag nodes:
i32 C = Constant<1>
v4i32 V = BUILD_VECTOR C, C, C, C
v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1
The SIGN_EXTEND_INREG node can be folded into a build_vector since
the vector in input is a BUILD_VECTOR of constants.
The optimized sequence is:
i32 C = Constant<-1>
v4i32 Result = BUILD_VECTOR C, C, C, C
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198084 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/2011-12-28-vselecti8.ll')
| -rw-r--r-- | test/CodeGen/X86/2011-12-28-vselecti8.ll | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/test/CodeGen/X86/2011-12-28-vselecti8.ll b/test/CodeGen/X86/2011-12-28-vselecti8.ll index dbc122ac6e..c91646640b 100644 --- a/test/CodeGen/X86/2011-12-28-vselecti8.ll +++ b/test/CodeGen/X86/2011-12-28-vselecti8.ll @@ -3,10 +3,20 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-darwin11.2.0" -; CHECK: @foo8 -; CHECK: psll -; CHECK: psraw -; CHECK: pblendvb +; During legalization, the vselect mask is 'type legalized' into a +; wider BUILD_VECTOR. This causes the introduction of a new +; sign_extend_inreg in the DAG. +; +; A sign_extend_inreg of a vector of ConstantSDNode or undef can be +; always folded into a simple build_vector. +; +; Make sure that the sign_extend_inreg is simplified and that we +; don't generate psll, psraw and pblendvb from the vselect. + +; CHECK-LABEL: foo8 +; CHECK-NOT: psll +; CHECK-NOT: psraw +; CHECK-NOT: pblendvb ; CHECK: ret define void @foo8(float* nocapture %RET) nounwind { allocas: @@ -17,4 +27,3 @@ allocas: ret void } - |