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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-20 19:35:22 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-20 19:35:22 +0000 |
| commit | 825b93b2dfb101c8b5e32d6f7199e116d559f625 (patch) | |
| tree | a179d49657b0f91c7183d13bc3ba03f0c9db5bb6 /test/CodeGen/X86/avx-blend.ll | |
| parent | 16d00e4b64ce2d2560f4f7e46517f3ce1e05bdf1 (diff) | |
| download | llvm-825b93b2dfb101c8b5e32d6f7199e116d559f625.tar.gz llvm-825b93b2dfb101c8b5e32d6f7199e116d559f625.tar.bz2 llvm-825b93b2dfb101c8b5e32d6f7199e116d559f625.tar.xz | |
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199683 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/avx-blend.ll')
| -rw-r--r-- | test/CodeGen/X86/avx-blend.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/X86/avx-blend.ll b/test/CodeGen/X86/avx-blend.ll index a98e0761ce..e9bfce663f 100644 --- a/test/CodeGen/X86/avx-blend.ll +++ b/test/CodeGen/X86/avx-blend.ll @@ -6,7 +6,7 @@ ;CHECK: vblendvps ;CHECK: ret define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { - %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2 + %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %v1, <4 x float> %v2 ret <4 x float> %vsel } @@ -15,13 +15,13 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { ;CHECK: vblendvps ;CHECK: ret define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) { - %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2 + %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %v1, <4 x i32> %v2 ret <4 x i32> %vsel } ;CHECK-LABEL: vsel_double: -;CHECK: vblendvpd +;CHECK: vmovsd ;CHECK: ret define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) { %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2 @@ -30,7 +30,7 @@ define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) { ;CHECK-LABEL: vsel_i64: -;CHECK: vblendvpd +;CHECK: vmovsd ;CHECK: ret define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) { %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2 |