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authorChad Rosier <mcrosier@apple.com>2012-03-09 02:00:48 +0000
committerChad Rosier <mcrosier@apple.com>2012-03-09 02:00:48 +0000
commitabd6674166d99a8da98269051fbd869d9d8c3ba1 (patch)
tree4b68f0ac12b9221bc2931e98600677d9a545ca4a /test/CodeGen/X86/avx-shuffle.ll
parentd04ec0c855176ebddd459c044bdd24f49938fae4 (diff)
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Fix a regression from r147481.
Original commit message from r147481: DAGCombine for transforming 128->256 casts into a vmovaps, rather then a vxorps + vinsertf128 pair if the original vector came from a load. Fix: Unaligned loads need to generate a vmovups. rdar://10974078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/avx-shuffle.ll')
-rw-r--r--test/CodeGen/X86/avx-shuffle.ll12
1 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx-shuffle.ll b/test/CodeGen/X86/avx-shuffle.ll
index 947d79f9e4..54f01e966d 100644
--- a/test/CodeGen/X86/avx-shuffle.ll
+++ b/test/CodeGen/X86/avx-shuffle.ll
@@ -135,3 +135,15 @@ define <4 x i32> @test15(<2 x i32>%x) nounwind readnone {
ret <4 x i32>%x1
}
+; rdar://10974078
+define <8 x float> @test16(float* nocapture %f) nounwind uwtable readonly ssp {
+entry:
+ %0 = bitcast float* %f to <4 x float>*
+ %1 = load <4 x float>* %0, align 8
+; CHECK: test16
+; CHECK: vmovups
+; CHECK-NOT: vxorps
+; CHECK-NOT: vinsertf128
+ %shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
+ ret <8 x float> %shuffle.i
+}