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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-17 18:58:01 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-17 18:58:01 +0000 |
| commit | 94bdb453a40e53e4318380b5a262ce3c324d10ce (patch) | |
| tree | ba016c94f7b6741830f594bb9c5890e235c182bc /test/CodeGen/X86/avx2-vector-shifts.ll | |
| parent | 63d93faa9b2a8a1a38758f9ca9cff79bc0cac5fc (diff) | |
| download | llvm-94bdb453a40e53e4318380b5a262ce3c324d10ce.tar.gz llvm-94bdb453a40e53e4318380b5a262ce3c324d10ce.tar.bz2 llvm-94bdb453a40e53e4318380b5a262ce3c324d10ce.tar.xz | |
Make DAGCombiner work on vector bitshifts with constant splat vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204071 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/avx2-vector-shifts.ll')
| -rw-r--r-- | test/CodeGen/X86/avx2-vector-shifts.ll | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/test/CodeGen/X86/avx2-vector-shifts.ll b/test/CodeGen/X86/avx2-vector-shifts.ll index 4868e4b479..4ae2905ef2 100644 --- a/test/CodeGen/X86/avx2-vector-shifts.ll +++ b/test/CodeGen/X86/avx2-vector-shifts.ll @@ -9,7 +9,7 @@ entry: } ; CHECK-LABEL: test_sllw_1: -; CHECK: vpsllw $0, %ymm0, %ymm0 +; CHECK-NOT: vpsllw $0, %ymm0, %ymm0 ; CHECK: ret define <16 x i16> @test_sllw_2(<16 x i16> %InVec) { @@ -39,7 +39,7 @@ entry: } ; CHECK-LABEL: test_slld_1: -; CHECK: vpslld $0, %ymm0, %ymm0 +; CHECK-NOT: vpslld $0, %ymm0, %ymm0 ; CHECK: ret define <8 x i32> @test_slld_2(<8 x i32> %InVec) { @@ -69,7 +69,7 @@ entry: } ; CHECK-LABEL: test_sllq_1: -; CHECK: vpsllq $0, %ymm0, %ymm0 +; CHECK-NOT: vpsllq $0, %ymm0, %ymm0 ; CHECK: ret define <4 x i64> @test_sllq_2(<4 x i64> %InVec) { @@ -101,7 +101,7 @@ entry: } ; CHECK-LABEL: test_sraw_1: -; CHECK: vpsraw $0, %ymm0, %ymm0 +; CHECK-NOT: vpsraw $0, %ymm0, %ymm0 ; CHECK: ret define <16 x i16> @test_sraw_2(<16 x i16> %InVec) { @@ -131,7 +131,7 @@ entry: } ; CHECK-LABEL: test_srad_1: -; CHECK: vpsrad $0, %ymm0, %ymm0 +; CHECK-NOT: vpsrad $0, %ymm0, %ymm0 ; CHECK: ret define <8 x i32> @test_srad_2(<8 x i32> %InVec) { @@ -163,7 +163,7 @@ entry: } ; CHECK-LABEL: test_srlw_1: -; CHECK: vpsrlw $0, %ymm0, %ymm0 +; CHECK-NOT: vpsrlw $0, %ymm0, %ymm0 ; CHECK: ret define <16 x i16> @test_srlw_2(<16 x i16> %InVec) { @@ -193,7 +193,7 @@ entry: } ; CHECK-LABEL: test_srld_1: -; CHECK: vpsrld $0, %ymm0, %ymm0 +; CHECK-NOT: vpsrld $0, %ymm0, %ymm0 ; CHECK: ret define <8 x i32> @test_srld_2(<8 x i32> %InVec) { @@ -223,7 +223,7 @@ entry: } ; CHECK-LABEL: test_srlq_1: -; CHECK: vpsrlq $0, %ymm0, %ymm0 +; CHECK-NOT: vpsrlq $0, %ymm0, %ymm0 ; CHECK: ret define <4 x i64> @test_srlq_2(<4 x i64> %InVec) { @@ -245,3 +245,14 @@ entry: ; CHECK-LABEL: test_srlq_3: ; CHECK: vpsrlq $63, %ymm0, %ymm0 ; CHECK: ret + +; CHECK-LABEL: @srl_trunc_and_v4i64 +; CHECK: vpand +; CHECK-NEXT: vpsrlvd +; CHECK: ret +define <4 x i32> @srl_trunc_and_v4i64(<4 x i32> %x, <4 x i64> %y) nounwind { + %and = and <4 x i64> %y, <i64 8, i64 8, i64 8, i64 8> + %trunc = trunc <4 x i64> %and to <4 x i32> + %sra = lshr <4 x i32> %x, %trunc + ret <4 x i32> %sra +} |