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| author | Dan Gohman <gohman@apple.com> | 2010-03-04 19:58:08 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2010-03-04 19:58:08 +0000 |
| commit | 0ef701e6ae816b0360e0a66e8b815ff875fe2a32 (patch) | |
| tree | 6a710bb4ee67da4fce0cc70455e84d1de65b4ffd /test/CodeGen/X86/bswap-inline-asm.ll | |
| parent | bfcc8e0a6636651fa1f13949ec2faf99068042f1 (diff) | |
| download | llvm-0ef701e6ae816b0360e0a66e8b815ff875fe2a32.tar.gz llvm-0ef701e6ae816b0360e0a66e8b815ff875fe2a32.tar.bz2 llvm-0ef701e6ae816b0360e0a66e8b815ff875fe2a32.tar.xz | |
Fix recognition of 16-bit bswap for C front-ends which emit the
clobber registers in a different order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97741 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/bswap-inline-asm.ll')
| -rw-r--r-- | test/CodeGen/X86/bswap-inline-asm.ll | 67 |
1 files changed, 65 insertions, 2 deletions
diff --git a/test/CodeGen/X86/bswap-inline-asm.ll b/test/CodeGen/X86/bswap-inline-asm.ll index 5bf58fa1d5..2b7019371a 100644 --- a/test/CodeGen/X86/bswap-inline-asm.ll +++ b/test/CodeGen/X86/bswap-inline-asm.ll @@ -1,17 +1,80 @@ ; RUN: llc < %s -march=x86-64 > %t ; RUN: not grep APP %t -; RUN: grep bswapq %t | count 2 -; RUN: grep bswapl %t | count 1 +; RUN: FileCheck %s < %t +; CHECK: foo: +; CHECK: bswapq define i64 @foo(i64 %x) nounwind { %asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind ret i64 %asmtmp } + +; CHECK: bar: +; CHECK: bswapq define i64 @bar(i64 %x) nounwind { %asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind ret i64 %asmtmp } + +; CHECK: pen: +; CHECK: bswapl define i32 @pen(i32 %x) nounwind { %asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind ret i32 %asmtmp } + +; CHECK: s16: +; CHECK: rolw $8, +define zeroext i16 @s16(i16 zeroext %x) nounwind { + %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind + ret i16 %asmtmp +} + +; CHECK: t16: +; CHECK: rolw $8, +define zeroext i16 @t16(i16 zeroext %x) nounwind { + %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind + ret i16 %asmtmp +} + +; CHECK: u16: +; CHECK: rolw $8, +define zeroext i16 @u16(i16 zeroext %x) nounwind { + %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind + ret i16 %asmtmp +} + +; CHECK: v16: +; CHECK: rolw $8, +define zeroext i16 @v16(i16 zeroext %x) nounwind { + %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind + ret i16 %asmtmp +} + +; CHECK: s32: +; CHECK: bswapl +define i32 @s32(i32 %x) nounwind { + %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind + ret i32 %asmtmp +} + +; CHECK: t32: +; CHECK: bswapl +define i32 @t32(i32 %x) nounwind { + %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind + ret i32 %asmtmp +} + +; CHECK: s64: +; CHECK: bswapq +define i64 @s64(i64 %x) nounwind { + %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind + ret i64 %asmtmp +} + +; CHECK: t64: +; CHECK: bswapq +define i64 @t64(i64 %x) nounwind { + %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{fpsr},~{dirflag},~{flags}"(i64 %x) nounwind + ret i64 %asmtmp +} |