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| author | Dan Gohman <gohman@apple.com> | 2009-01-13 23:23:30 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-01-13 23:23:30 +0000 |
| commit | f31408d75c42f48041e40aaaee147dcaa8477bc0 (patch) | |
| tree | 5527524441bb600ed30ea51f78b7cf62738ae956 /test/CodeGen/X86/bt.ll | |
| parent | e2051627b81c713fd29f61ce6d4424d0388cc37d (diff) | |
| download | llvm-f31408d75c42f48041e40aaaee147dcaa8477bc0.tar.gz llvm-f31408d75c42f48041e40aaaee147dcaa8477bc0.tar.bz2 llvm-f31408d75c42f48041e40aaaee147dcaa8477bc0.tar.xz | |
Disable the register+memory forms of the bt instructions for now. Thanks
to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62194 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/bt.ll')
| -rw-r--r-- | test/CodeGen/X86/bt.ll | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/test/CodeGen/X86/bt.ll b/test/CodeGen/X86/bt.ll index b63a3f8ecf..86254d3295 100644 --- a/test/CodeGen/X86/bt.ll +++ b/test/CodeGen/X86/bt.ll @@ -1,7 +1,12 @@ ; RUN: llvm-as < %s | llc | grep btl -; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | grep esp +; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | not grep esp ; RUN: llvm-as < %s | llc -mcpu=penryn | grep btl | not grep esp ; PR3253 + +; The register+memory form of the BT instruction should be usable on +; pentium4, however it is currently disabled due to the register+memory +; form having different semantics than the register+register form. + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" |