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authorEvan Cheng <evan.cheng@apple.com>2009-01-02 05:35:45 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-01-02 05:35:45 +0000
commitccb6976a69a6e146db049fff8e6338e31c91b6f8 (patch)
treeb17dc585023e3b05a5f8b7a243aa0c68cc76ce46 /test/CodeGen/X86/bt.ll
parent018b7ee91a1dc8e1f87ea8c9133b5e44d9e57972 (diff)
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Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/bt.ll')
-rw-r--r--test/CodeGen/X86/bt.ll2
1 files changed, 2 insertions, 0 deletions
diff --git a/test/CodeGen/X86/bt.ll b/test/CodeGen/X86/bt.ll
index bc77a58ce2..b63a3f8ecf 100644
--- a/test/CodeGen/X86/bt.ll
+++ b/test/CodeGen/X86/bt.ll
@@ -1,4 +1,6 @@
; RUN: llvm-as < %s | llc | grep btl
+; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | grep esp
+; RUN: llvm-as < %s | llc -mcpu=penryn | grep btl | not grep esp
; PR3253
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"