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| author | Shuxin Yang <shuxin.llvm@gmail.com> | 2013-03-25 22:52:29 +0000 |
|---|---|---|
| committer | Shuxin Yang <shuxin.llvm@gmail.com> | 2013-03-25 22:52:29 +0000 |
| commit | 1cd1d02141788b212e185d190b4c358e47cc74b4 (patch) | |
| tree | fa0982071c8d36376f6fa7a562c247805d826b60 /test/CodeGen/X86/dagcombine_unsafe_math.ll | |
| parent | 3800f5748ffdb55d8838eac9300d84276c3dd2c1 (diff) | |
| download | llvm-1cd1d02141788b212e185d190b4c358e47cc74b4.tar.gz llvm-1cd1d02141788b212e185d190b4c358e47cc74b4.tar.bz2 llvm-1cd1d02141788b212e185d190b4c358e47cc74b4.tar.xz | |
Disable some unsafe-fp-math DAG-combine transformation after legalization.
For instance, following transformation will be disabled:
x + x + x => 3.0f * x;
The problem of these transformations is that it introduces a FP constant, which
following Instruction-Selection pass cannot handle.
Reviewed by Nadav, thanks a lot!
rdar://13445387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177933 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/dagcombine_unsafe_math.ll')
| -rw-r--r-- | test/CodeGen/X86/dagcombine_unsafe_math.ll | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/test/CodeGen/X86/dagcombine_unsafe_math.ll b/test/CodeGen/X86/dagcombine_unsafe_math.ll index a3221dea5b..592cf1bec2 100644 --- a/test/CodeGen/X86/dagcombine_unsafe_math.ll +++ b/test/CodeGen/X86/dagcombine_unsafe_math.ll @@ -40,3 +40,17 @@ define float @test4(float %x, float %y) { ; CHECK: test4 ; CHECK: vaddss } + +; rdar://13445387 +; "x + x + x => 3.0 * x" should be disabled after legalization because +; Instruction-Selection dosen't know how to handle "3.0" +; +define float @test5() { + %mul.i.i151 = fmul <4 x float> zeroinitializer, zeroinitializer + %vecext.i8.i152 = extractelement <4 x float> %mul.i.i151, i32 1 + %vecext1.i9.i153 = extractelement <4 x float> %mul.i.i151, i32 0 + %add.i10.i154 = fadd float %vecext1.i9.i153, %vecext.i8.i152 + %vecext.i7.i155 = extractelement <4 x float> %mul.i.i151, i32 2 + %add.i.i156 = fadd float %vecext.i7.i155, %add.i10.i154 + ret float %add.i.i156 +} |