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| author | Stephen Lin <stephenwlin@gmail.com> | 2013-07-13 20:38:47 +0000 |
|---|---|---|
| committer | Stephen Lin <stephenwlin@gmail.com> | 2013-07-13 20:38:47 +0000 |
| commit | b4dc0233c9f70e8cf946822811f233bb613a02e9 (patch) | |
| tree | 6cb47482e15d250ae95e5c6c96abd2afb56f6fca /test/CodeGen/X86/fast-isel-divrem.ll | |
| parent | ae4e1a94e3fb7d1d2d0eec6eb7d04b74326c8453 (diff) | |
| download | llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.gz llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.bz2 llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.xz | |
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries:
sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/fast-isel-divrem.ll')
| -rw-r--r-- | test/CodeGen/X86/fast-isel-divrem.ll | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/CodeGen/X86/fast-isel-divrem.ll b/test/CodeGen/X86/fast-isel-divrem.ll index 1a309a1ebc..5828becb3c 100644 --- a/test/CodeGen/X86/fast-isel-divrem.ll +++ b/test/CodeGen/X86/fast-isel-divrem.ll @@ -7,7 +7,7 @@ entry: ret i8 %result } -; CHECK: test_sdiv8: +; CHECK-LABEL: test_sdiv8: ; CHECK: movsbw ; CHECK: idivb @@ -17,7 +17,7 @@ entry: ret i8 %result } -; CHECK: test_srem8: +; CHECK-LABEL: test_srem8: ; CHECK: movsbw ; CHECK: idivb @@ -27,7 +27,7 @@ entry: ret i8 %result } -; CHECK: test_udiv8: +; CHECK-LABEL: test_udiv8: ; CHECK: movzbw ; CHECK: divb @@ -37,7 +37,7 @@ entry: ret i8 %result } -; CHECK: test_urem8: +; CHECK-LABEL: test_urem8: ; CHECK: movzbw ; CHECK: divb @@ -47,7 +47,7 @@ entry: ret i16 %result } -; CHECK: test_sdiv16: +; CHECK-LABEL: test_sdiv16: ; CHECK: cwtd ; CHECK: idivw @@ -57,7 +57,7 @@ entry: ret i16 %result } -; CHECK: test_srem16: +; CHECK-LABEL: test_srem16: ; CHECK: cwtd ; CHECK: idivw @@ -67,7 +67,7 @@ entry: ret i16 %result } -; CHECK: test_udiv16: +; CHECK-LABEL: test_udiv16: ; CHECK: xorl ; CHECK: divw @@ -77,7 +77,7 @@ entry: ret i16 %result } -; CHECK: test_urem16: +; CHECK-LABEL: test_urem16: ; CHECK: xorl ; CHECK: divw @@ -87,7 +87,7 @@ entry: ret i32 %result } -; CHECK: test_sdiv32: +; CHECK-LABEL: test_sdiv32: ; CHECK: cltd ; CHECK: idivl @@ -97,7 +97,7 @@ entry: ret i32 %result } -; CHECK: test_srem32: +; CHECK-LABEL: test_srem32: ; CHECK: cltd ; CHECK: idivl @@ -107,7 +107,7 @@ entry: ret i32 %result } -; CHECK: test_udiv32: +; CHECK-LABEL: test_udiv32: ; CHECK: xorl ; CHECK: divl @@ -117,6 +117,6 @@ entry: ret i32 %result } -; CHECK: test_urem32: +; CHECK-LABEL: test_urem32: ; CHECK: xorl ; CHECK: divl |