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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2012-04-27 12:07:43 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2012-04-27 12:07:43 +0000 |
| commit | 17c836c4b51a14f07a5d5442cf2e984474a8f57d (patch) | |
| tree | 74181d3329eae68c0137d0d18c5ce2db3ff901fe /test/CodeGen/X86/fp-stack-compare-cmov.ll | |
| parent | c84f975e6fa65049ecd3268f830218e791893efd (diff) | |
| download | llvm-17c836c4b51a14f07a5d5442cf2e984474a8f57d.tar.gz llvm-17c836c4b51a14f07a5d5442cf2e984474a8f57d.tar.bz2 llvm-17c836c4b51a14f07a5d5442cf2e984474a8f57d.tar.xz | |
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/fp-stack-compare-cmov.ll')
| -rw-r--r-- | test/CodeGen/X86/fp-stack-compare-cmov.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/X86/fp-stack-compare-cmov.ll b/test/CodeGen/X86/fp-stack-compare-cmov.ll new file mode 100644 index 0000000000..b457fbc1a3 --- /dev/null +++ b/test/CodeGen/X86/fp-stack-compare-cmov.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s +; PR1012 + +define float @foo(float* %col.2.0) { +; CHECK: fucompi +; CHECK: fcmov + %tmp = load float* %col.2.0 + %tmp16 = fcmp olt float %tmp, 0.000000e+00 + %tmp20 = fsub float -0.000000e+00, %tmp + %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp + ret float %iftmp.2.0 +} |