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| author | Dan Gohman <gohman@apple.com> | 2009-08-05 17:40:24 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-08-05 17:40:24 +0000 |
| commit | 74f6f9a931e313948782aed9d463ea83cc3e214c (patch) | |
| tree | c5cd8c1c80e29cb3eade756e7eb7d8c0c162351d /test/CodeGen/X86/ins_subreg_coalesce-3.ll | |
| parent | 7f0f2515a01596a2785aca9ee5f630ecc0ab134a (diff) | |
| download | llvm-74f6f9a931e313948782aed9d463ea83cc3e214c.tar.gz llvm-74f6f9a931e313948782aed9d463ea83cc3e214c.tar.bz2 llvm-74f6f9a931e313948782aed9d463ea83cc3e214c.tar.xz | |
Enable the new no-SP register classes by default. This is to address
PR4572. A few tests have some minor code regressions due to different
coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78217 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/ins_subreg_coalesce-3.ll')
| -rw-r--r-- | test/CodeGen/X86/ins_subreg_coalesce-3.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-3.ll b/test/CodeGen/X86/ins_subreg_coalesce-3.ll index 6fd18d6541..3213723db0 100644 --- a/test/CodeGen/X86/ins_subreg_coalesce-3.ll +++ b/test/CodeGen/X86/ins_subreg_coalesce-3.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 10 +; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 11 %struct.COMPOSITE = type { i8, i16, i16 } %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } |