diff options
| author | Duncan Sands <baldrick@free.fr> | 2011-11-09 14:20:48 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2011-11-09 14:20:48 +0000 |
| commit | ef0b3ca3a8935b5390633dc7bb4adcdb99e0c26a (patch) | |
| tree | 80f00ee91cc70c723998460fe67d10d745d01ae6 /test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll | |
| parent | bb539bf973bb861ffe8179ac8791fad19448cd52 (diff) | |
| download | llvm-ef0b3ca3a8935b5390633dc7bb4adcdb99e0c26a.tar.gz llvm-ef0b3ca3a8935b5390633dc7bb4adcdb99e0c26a.tar.bz2 llvm-ef0b3ca3a8935b5390633dc7bb4adcdb99e0c26a.tar.xz | |
Speculatively revert commit 144124 (djg) in the hope that the 32 bit
dragonegg self-host buildbot will recover (it is complaining about object
files differing between different build stages). Original commit message:
Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144188 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll')
| -rw-r--r-- | test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll b/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll deleted file mode 100644 index b114a57966..0000000000 --- a/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc -march=x86 -mcpu=pentium4 -mtriple=i686-none-linux < %s -; PR11314 - -; Make sure the scheduler's hack to insert artificial dependencies to optimize -; two-address instruction scheduling doesn't interfere with the scheduler's -; hack to model call sequences as artificial physical registers. - -define inreg { i64, i64 } @sscanf(i32 inreg %base.1.i) nounwind { -entry: - %conv38.i92.i = sext i32 %base.1.i to i64 - %rem.i93.i = urem i64 10, %conv38.i92.i - %div.i94.i = udiv i64 10, %conv38.i92.i - %a = insertvalue { i64, i64 } undef, i64 %rem.i93.i, 0 - %b = insertvalue { i64, i64 } %a, i64 %div.i94.i, 1 - ret { i64, i64 } %b -} |