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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2014-05-06 17:09:03 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2014-05-06 17:09:03 +0000
commit8a712ba229f506ff2d25d75cf2e2fcd980ee0834 (patch)
tree6f546e75b9366105ee6827fa0907857c0c2ec368 /test/CodeGen/X86/ret-mmx.ll
parent22f779d1fd0d7a7e878a3c28bc5d9910ae655df3 (diff)
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[X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 (and vice versa).
Before this patch, the backend always emitted a store+load sequence to bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting i64 node was then used to build a v2i32 vector. With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free" bitcast to type MVT::v4i32. The elements of the resulting v4i32 are then extracted to build a v2i32 vector (which is illegal and therefore promoted to MVT::v2i64). This is in general cheaper than emitting a stack store+load sequence to bitconvert the operand from type f64 to type i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208107 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/ret-mmx.ll')
-rw-r--r--test/CodeGen/X86/ret-mmx.ll5
1 files changed, 3 insertions, 2 deletions
diff --git a/test/CodeGen/X86/ret-mmx.ll b/test/CodeGen/X86/ret-mmx.ll
index 091fd53984..7adf307ce0 100644
--- a/test/CodeGen/X86/ret-mmx.ll
+++ b/test/CodeGen/X86/ret-mmx.ll
@@ -33,7 +33,8 @@ define <2 x i32> @t3() nounwind {
define double @t4() nounwind {
ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
; CHECK-LABEL: t4:
-; CHECK: movl $1
-; CHECK: movd {{.*}}, %xmm0
+; CHECK-NOT: movl $1
+; CHECK-NOT: pshufd
+; CHECK: movsd {{.*}}, %xmm0
}