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author | Chandler Carruth <chandlerc@gmail.com> | 2012-12-11 00:36:57 +0000 |
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committer | Chandler Carruth <chandlerc@gmail.com> | 2012-12-11 00:36:57 +0000 |
commit | 1c49fda408ae5ba90fdaf1b274edd1119aea58b7 (patch) | |
tree | 69f6d081c4252c86b2c3655fd4b2aa2afce24064 /test/CodeGen/X86/sext-load.ll | |
parent | 0a0990af1c525b0f16c4e7989eae8e3324ddf95a (diff) | |
download | llvm-1c49fda408ae5ba90fdaf1b274edd1119aea58b7.tar.gz llvm-1c49fda408ae5ba90fdaf1b274edd1119aea58b7.tar.bz2 llvm-1c49fda408ae5ba90fdaf1b274edd1119aea58b7.tar.xz |
Fix a miscompile in the DAG combiner. Previously, we would incorrectly
try to reduce the width of this load, and would end up transforming:
(truncate (lshr (sextload i48 <ptr> as i64), 32) to i32)
to
(truncate (zextload i32 <ptr+4> as i64) to i32)
We lost the sext attached to the load while building the narrower i32
load, and replaced it with a zext because lshr always zext's the
results. Instead, bail out of this combine when there is a conflict
between a sextload and a zext narrowing. The rest of the DAG combiner
still optimize the code down to the proper single instruction:
movswl 6(...),%eax
Which is exactly what we wanted. Previously we read past the end *and*
missed the sign extension:
movl 6(...), %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169802 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/sext-load.ll')
-rw-r--r-- | test/CodeGen/X86/sext-load.ll | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/test/CodeGen/X86/sext-load.ll b/test/CodeGen/X86/sext-load.ll index c9b39d3a48..58c93229a2 100644 --- a/test/CodeGen/X86/sext-load.ll +++ b/test/CodeGen/X86/sext-load.ll @@ -1,9 +1,30 @@ -; RUN: llc < %s -march=x86 | grep movsbl +; RUN: llc < %s -march=x86 | FileCheck %s -define i32 @foo(i32 %X) nounwind { +; When doing sign extension, use the sext-load lowering to take advantage of +; x86's sign extension during loads. +; +; CHECK: test1: +; CHECK: movsbl {{.*}}, %eax +; CHECK-NEXT: ret +define i32 @test1(i32 %X) nounwind { entry: %tmp12 = trunc i32 %X to i8 ; <i8> [#uses=1] %tmp123 = sext i8 %tmp12 to i32 ; <i32> [#uses=1] ret i32 %tmp123 } +; When using a sextload representation, ensure that the sign extension is +; preserved even when removing shifted-out low bits. +; +; CHECK: test2: +; CHECK: movswl {{.*}}, %eax +; CHECK-NEXT: ret +define i32 @test2({i16, [6 x i8]}* %this) { +entry: + %b48 = getelementptr inbounds { i16, [6 x i8] }* %this, i32 0, i32 1 + %cast = bitcast [6 x i8]* %b48 to i48* + %bf.load = load i48* %cast, align 2 + %bf.ashr = ashr i48 %bf.load, 32 + %bf.cast = trunc i48 %bf.ashr to i32 + ret i32 %bf.cast +} |