Fixed the encoding problems of the crc32 instructions. All had the Operand size

override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 6 deletions

diff --git a/test/CodeGen/X86/sse42.ll b/test/CodeGen/X86/sse42.ll
index c9c4d01210..1723909a4b 100644
--- a/test/CodeGen/X86/sse42.ll
+++ b/test/CodeGen/X86/sse42.ll
@@ -9,10 +9,10 @@ define i32 @crc32_8(i32 %a, i8 %b) nounwind {
   %tmp = call i32 @llvm.x86.sse42.crc32.8(i32 %a, i8 %b)
   ret i32 %tmp
 ; X32: _crc32_8:
-; X32:     crc32   8(%esp), %eax
+; X32:     crc32b   8(%esp), %eax
 
 ; X64: _crc32_8:
-; X64:     crc32   %sil, %eax
+; X64:     crc32b   %sil, %eax
 }
 
 
@@ -20,10 +20,10 @@ define i32 @crc32_16(i32 %a, i16 %b) nounwind {
   %tmp = call i32 @llvm.x86.sse42.crc32.16(i32 %a, i16 %b)
   ret i32 %tmp
 ; X32: _crc32_16:
-; X32:     crc32   8(%esp), %eax
+; X32:     crc32w   8(%esp), %eax
 
 ; X64: _crc32_16:
-; X64:     crc32   %si, %eax
+; X64:     crc32w   %si, %eax
 }
 
 
@@ -31,8 +31,8 @@ define i32 @crc32_32(i32 %a, i32 %b) nounwind {
   %tmp = call i32 @llvm.x86.sse42.crc32.32(i32 %a, i32 %b)
   ret i32 %tmp
 ; X32: _crc32_32:
-; X32:     crc32   8(%esp), %eax
+; X32:     crc32l   8(%esp), %eax
 
 ; X64: _crc32_32:
-; X64:     crc32   %esi, %eax
+; X64:     crc32l   %esi, %eax
 }