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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-04-02 22:30:39 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-04-02 22:30:39 +0000 |
| commit | e3b23cde80b19507f1d8b641a541e91ace0864dc (patch) | |
| tree | 10806194e6d64949fd2dd95d36f75211a6c7f84c /test/CodeGen/X86/store_op_load_fold2.ll | |
| parent | 8a06af96698537377275dd7848db69915638dd26 (diff) | |
| download | llvm-e3b23cde80b19507f1d8b641a541e91ace0864dc.tar.gz llvm-e3b23cde80b19507f1d8b641a541e91ace0864dc.tar.bz2 llvm-e3b23cde80b19507f1d8b641a541e91ace0864dc.tar.xz | |
Allocate virtual registers in ascending order.
This is just the fallback tie-breaker ordering, the main allocation
order is still descending size.
Patch by Shamil Kurmangaleev!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153904 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/store_op_load_fold2.ll')
| -rw-r--r-- | test/CodeGen/X86/store_op_load_fold2.ll | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/test/CodeGen/X86/store_op_load_fold2.ll b/test/CodeGen/X86/store_op_load_fold2.ll index 11686227ab..8313166a90 100644 --- a/test/CodeGen/X86/store_op_load_fold2.ll +++ b/test/CodeGen/X86/store_op_load_fold2.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=i686-linux -x86-asm-syntax=intel | FileCheck %s +; RUN: llc < %s -mtriple=i686-linux -x86-asm-syntax=att | FileCheck %s -check-prefix=ATT +; RUN: llc < %s -mtriple=i686-linux -x86-asm-syntax=intel | FileCheck %s -check-prefix=INTEL target datalayout = "e-p:32:32" %struct.Macroblock = type { i32, i32, i32, i32, i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 } @@ -16,9 +17,14 @@ cond_true2732.preheader: ; preds = %entry store i64 %tmp2676.us.us, i64* %tmp2666 ret i32 0 -; CHECK: and {{E..}}, DWORD PTR [360] -; CHECK: and DWORD PTR [356], {{E..}} -; CHECK: mov DWORD PTR [360], {{E..}} +; INTEL: and {{E..}}, DWORD PTR [360] +; INTEL: and DWORD PTR [356], {{E..}} +; FIXME: mov DWORD PTR [360], {{E..}} +; The above line comes out as 'mov 360, EAX', but when the register is ECX it works? + +; ATT: andl 360, %{{e..}} +; ATT: andl %{{e..}}, 356 +; ATT: movl %{{e..}}, 360 } |