diff options
author | Stephen Lin <stephenwlin@gmail.com> | 2013-07-13 20:38:47 +0000 |
---|---|---|
committer | Stephen Lin <stephenwlin@gmail.com> | 2013-07-13 20:38:47 +0000 |
commit | b4dc0233c9f70e8cf946822811f233bb613a02e9 (patch) | |
tree | 6cb47482e15d250ae95e5c6c96abd2afb56f6fca /test/CodeGen/X86/viabs.ll | |
parent | ae4e1a94e3fb7d1d2d0eec6eb7d04b74326c8453 (diff) | |
download | llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.gz llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.bz2 llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.xz |
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries:
sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/viabs.ll')
-rw-r--r-- | test/CodeGen/X86/viabs.ll | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/test/CodeGen/X86/viabs.ll b/test/CodeGen/X86/viabs.ll index f748a14836..0be00da83f 100644 --- a/test/CodeGen/X86/viabs.ll +++ b/test/CodeGen/X86/viabs.ll @@ -3,18 +3,18 @@ ; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2 define <4 x i32> @test1(<4 x i32> %a) nounwind { -; SSE2: test1: +; SSE2-LABEL: test1: ; SSE2: movdqa ; SSE2: psrad $31 ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test1: +; SSSE3-LABEL: test1: ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test1: +; AVX2-LABEL: test1: ; AVX2: vpabsd ; AVX2-NEXT: ret %tmp1neg = sub <4 x i32> zeroinitializer, %a @@ -24,18 +24,18 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind { } define <4 x i32> @test2(<4 x i32> %a) nounwind { -; SSE2: test2: +; SSE2-LABEL: test2: ; SSE2: movdqa ; SSE2: psrad $31 ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test2: +; SSSE3-LABEL: test2: ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test2: +; AVX2-LABEL: test2: ; AVX2: vpabsd ; AVX2-NEXT: ret %tmp1neg = sub <4 x i32> zeroinitializer, %a @@ -45,18 +45,18 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind { } define <8 x i16> @test3(<8 x i16> %a) nounwind { -; SSE2: test3: +; SSE2-LABEL: test3: ; SSE2: movdqa ; SSE2: psraw $15 ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test3: +; SSSE3-LABEL: test3: ; SSSE3: pabsw ; SSSE3-NEXT: ret -; AVX2: test3: +; AVX2-LABEL: test3: ; AVX2: vpabsw ; AVX2-NEXT: ret %tmp1neg = sub <8 x i16> zeroinitializer, %a @@ -66,18 +66,18 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind { } define <16 x i8> @test4(<16 x i8> %a) nounwind { -; SSE2: test4: +; SSE2-LABEL: test4: ; SSE2: pxor ; SSE2: pcmpgtb ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test4: +; SSSE3-LABEL: test4: ; SSSE3: pabsb ; SSSE3-NEXT: ret -; AVX2: test4: +; AVX2-LABEL: test4: ; AVX2: vpabsb ; AVX2-NEXT: ret %tmp1neg = sub <16 x i8> zeroinitializer, %a @@ -87,18 +87,18 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind { } define <4 x i32> @test5(<4 x i32> %a) nounwind { -; SSE2: test5: +; SSE2-LABEL: test5: ; SSE2: movdqa ; SSE2: psrad $31 ; SSE2-NEXT: padd ; SSE2-NEXT: pxor ; SSE2-NEXT: ret -; SSSE3: test5: +; SSSE3-LABEL: test5: ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test5: +; AVX2-LABEL: test5: ; AVX2: vpabsd ; AVX2-NEXT: ret %tmp1neg = sub <4 x i32> zeroinitializer, %a @@ -108,12 +108,12 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind { } define <8 x i32> @test6(<8 x i32> %a) nounwind { -; SSSE3: test6: +; SSSE3-LABEL: test6: ; SSSE3: pabsd ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test6: +; AVX2-LABEL: test6: ; AVX2: vpabsd {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <8 x i32> zeroinitializer, %a @@ -123,12 +123,12 @@ define <8 x i32> @test6(<8 x i32> %a) nounwind { } define <8 x i32> @test7(<8 x i32> %a) nounwind { -; SSSE3: test7: +; SSSE3-LABEL: test7: ; SSSE3: pabsd ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test7: +; AVX2-LABEL: test7: ; AVX2: vpabsd {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <8 x i32> zeroinitializer, %a @@ -138,12 +138,12 @@ define <8 x i32> @test7(<8 x i32> %a) nounwind { } define <16 x i16> @test8(<16 x i16> %a) nounwind { -; SSSE3: test8: +; SSSE3-LABEL: test8: ; SSSE3: pabsw ; SSSE3: pabsw ; SSSE3-NEXT: ret -; AVX2: test8: +; AVX2-LABEL: test8: ; AVX2: vpabsw {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <16 x i16> zeroinitializer, %a @@ -153,12 +153,12 @@ define <16 x i16> @test8(<16 x i16> %a) nounwind { } define <32 x i8> @test9(<32 x i8> %a) nounwind { -; SSSE3: test9: +; SSSE3-LABEL: test9: ; SSSE3: pabsb ; SSSE3: pabsb ; SSSE3-NEXT: ret -; AVX2: test9: +; AVX2-LABEL: test9: ; AVX2: vpabsb {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <32 x i8> zeroinitializer, %a @@ -168,12 +168,12 @@ define <32 x i8> @test9(<32 x i8> %a) nounwind { } define <8 x i32> @test10(<8 x i32> %a) nounwind { -; SSSE3: test10: +; SSSE3-LABEL: test10: ; SSSE3: pabsd ; SSSE3: pabsd ; SSSE3-NEXT: ret -; AVX2: test10: +; AVX2-LABEL: test10: ; AVX2: vpabsd {{.*}}%ymm ; AVX2-NEXT: ret %tmp1neg = sub <8 x i32> zeroinitializer, %a |