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| author | Dan Gohman <gohman@apple.com> | 2008-07-30 18:09:17 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-07-30 18:09:17 +0000 |
| commit | 11ba3b1af67796dabec10c70e16a93685e130719 (patch) | |
| tree | 8db7f1a3afe872f89bd2dcc733b8aed00b4df128 /test/CodeGen/X86/zext-inreg-0.ll | |
| parent | 912923925f790427a77781b8a0469fa832c7740d (diff) | |
| download | llvm-11ba3b1af67796dabec10c70e16a93685e130719.tar.gz llvm-11ba3b1af67796dabec10c70e16a93685e130719.tar.bz2 llvm-11ba3b1af67796dabec10c70e16a93685e130719.tar.xz | |
Reapply r54147 with a constraint to only use the 8-bit
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.
Also, change several 16-bit instructions to use
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/zext-inreg-0.ll')
| -rw-r--r-- | test/CodeGen/X86/zext-inreg-0.ll | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/test/CodeGen/X86/zext-inreg-0.ll b/test/CodeGen/X86/zext-inreg-0.ll new file mode 100644 index 0000000000..62c651c835 --- /dev/null +++ b/test/CodeGen/X86/zext-inreg-0.ll @@ -0,0 +1,51 @@ +; RUN: llvm-as < %s | llc -march=x86 | not grep and +; RUN: llvm-as < %s | llc -march=x86-64 > %t +; RUN: not grep and %t +; RUN: not grep movzbq %t +; RUN: not grep movzwq %t +; RUN: not grep movzlq %t + +; These should use movzbl instead of 'and 255'. +; This related to not having a ZERO_EXTEND_REG opcode. + +define i32 @c(i32 %d) nounwind { + %e = add i32 %d, 1 + %retval = and i32 %e, 65535 + ret i32 %retval +} +define i64 @e(i64 %d) nounwind { + %e = add i64 %d, 1 + %retval = and i64 %e, 65535 + ret i64 %retval +} +define i64 @f(i64 %d) nounwind { + %e = add i64 %d, 1 + %retval = and i64 %e, 4294967295 + ret i64 %retval +} + +define i32 @g(i8 %d) nounwind { + %e = add i8 %d, 1 + %retval = zext i8 %e to i32 + ret i32 %retval +} +define i32 @h(i16 %d) nounwind { + %e = add i16 %d, 1 + %retval = zext i16 %e to i32 + ret i32 %retval +} +define i64 @i(i8 %d) nounwind { + %e = add i8 %d, 1 + %retval = zext i8 %e to i64 + ret i64 %retval +} +define i64 @j(i16 %d) nounwind { + %e = add i16 %d, 1 + %retval = zext i16 %e to i64 + ret i64 %retval +} +define i64 @k(i32 %d) nounwind { + %e = add i32 %d, 1 + %retval = zext i32 %e to i64 + ret i64 %retval +} |