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| author | Dan Gohman <gohman@apple.com> | 2008-08-06 18:27:21 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-06 18:27:21 +0000 |
| commit | 8a1510d19228f3cb1a847c21fa9e678a565247f7 (patch) | |
| tree | 80801ca9ac3e70d8fe5f3a491a95b823cc71b85a /test/CodeGen/X86/zext-inreg-0.ll | |
| parent | 4ce9627e97094163f8a55cf0cb74f074bd17dfc8 (diff) | |
| download | llvm-8a1510d19228f3cb1a847c21fa9e678a565247f7.tar.gz llvm-8a1510d19228f3cb1a847c21fa9e678a565247f7.tar.bz2 llvm-8a1510d19228f3cb1a847c21fa9e678a565247f7.tar.xz | |
Re-introduce the 8-bit subreg zext-inreg patterns for x86-32,
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54418 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/zext-inreg-0.ll')
| -rw-r--r-- | test/CodeGen/X86/zext-inreg-0.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/test/CodeGen/X86/zext-inreg-0.ll b/test/CodeGen/X86/zext-inreg-0.ll index 62c651c835..1a734642d0 100644 --- a/test/CodeGen/X86/zext-inreg-0.ll +++ b/test/CodeGen/X86/zext-inreg-0.ll @@ -8,11 +8,26 @@ ; These should use movzbl instead of 'and 255'. ; This related to not having a ZERO_EXTEND_REG opcode. +define i32 @a(i32 %d) nounwind { + %e = add i32 %d, 1 + %retval = and i32 %e, 255 + ret i32 %retval +} +define i32 @b(float %d) nounwind { + %tmp12 = fptoui float %d to i8 + %retval = zext i8 %tmp12 to i32 + ret i32 %retval +} define i32 @c(i32 %d) nounwind { %e = add i32 %d, 1 %retval = and i32 %e, 65535 ret i32 %retval } +define i64 @d(i64 %d) nounwind { + %e = add i64 %d, 1 + %retval = and i64 %e, 255 + ret i64 %retval +} define i64 @e(i64 %d) nounwind { %e = add i64 %d, 1 %retval = and i64 %e, 65535 |