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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-29 21:23:04 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-29 21:23:04 +0000 |
| commit | b00418af67b36dcd7d70a268ebba3480c1011348 (patch) | |
| tree | bf0c4b39d2d831774d5ec7b7a182a2c29fb3c3f9 /test/CodeGen/X86 | |
| parent | f86545ecfdb48a43e62ce7dfd312913b0a24240b (diff) | |
| download | llvm-b00418af67b36dcd7d70a268ebba3480c1011348.tar.gz llvm-b00418af67b36dcd7d70a268ebba3480c1011348.tar.bz2 llvm-b00418af67b36dcd7d70a268ebba3480c1011348.tar.xz | |
Add a new DAGCombine optimization for BUILD_VECTOR.
If all of the inputs are zero/any_extended, create a new simple BV
which can be further optimized by other BV optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143297 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86')
| -rw-r--r-- | test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/2011-10-27-tstore.ll | 16 | ||||
| -rw-r--r-- | test/CodeGen/X86/vec_shuffle-37.ll | 10 |
3 files changed, 23 insertions, 5 deletions
diff --git a/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll b/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll index 025ab2e7c1..63a7da8755 100644 --- a/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll +++ b/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux -mattr=+mmx | grep movd | count 3 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+mmx | grep movd | count 2 define i64 @a(i32 %a, i32 %b) nounwind readnone { entry: diff --git a/test/CodeGen/X86/2011-10-27-tstore.ll b/test/CodeGen/X86/2011-10-27-tstore.ll new file mode 100644 index 0000000000..016e02c3d5 --- /dev/null +++ b/test/CodeGen/X86/2011-10-27-tstore.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s + +target triple = "x86_64-unknown-linux-gnu" + +;CHECK: ltstore +;CHECK: pshufd +;CHECK: pshufd +;CHECK: ret +define void @ltstore() { +entry: + %in = load <4 x i32>* undef + %j = shufflevector <4 x i32> %in, <4 x i32> undef, <2 x i32> <i32 0, i32 1> + store <2 x i32> %j, <2 x i32>* undef + ret void +} + diff --git a/test/CodeGen/X86/vec_shuffle-37.ll b/test/CodeGen/X86/vec_shuffle-37.ll index e91a7347cc..0608398938 100644 --- a/test/CodeGen/X86/vec_shuffle-37.ll +++ b/test/CodeGen/X86/vec_shuffle-37.ll @@ -26,10 +26,12 @@ entry: define void @t02(<8 x i32>* %source, <2 x i32>* %dest) nounwind noinline { entry: -; CHECK: movl 36({{%rdi|%rcx}}) -; CHECK-NEXT: movl 48({{%rdi|%rcx}}) -; CHECK: punpcklqdq -; CHECK: movq %xmm0, ({{%rsi|%rdx}}) +; CHECK: t02 +; CHECK: movaps +; CHECK: shufps +; CHECK: pshufd +; CHECK: movq +; CHECK: ret %0 = bitcast <8 x i32>* %source to <4 x i32>* %arrayidx = getelementptr inbounds <4 x i32>* %0, i64 3 %tmp2 = load <4 x i32>* %arrayidx, align 16 |