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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-09 12:32:53 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-09 12:32:53 +0000 |
commit | bc72c8f0d8dbab5e1ce748cc390254a06e9a5c0a (patch) | |
tree | 81bf525a15db395c1e6d19c294fa4dc4c4a21960 /test/CodeGen/X86 | |
parent | a2bc6951a028412e7af5e68aa369daa4611147b3 (diff) | |
download | llvm-bc72c8f0d8dbab5e1ce748cc390254a06e9a5c0a.tar.gz llvm-bc72c8f0d8dbab5e1ce748cc390254a06e9a5c0a.tar.bz2 llvm-bc72c8f0d8dbab5e1ce748cc390254a06e9a5c0a.tar.xz |
[DAG] Expose NoSignedWrap, NoUnsignedWrap and Exact flags to SelectionDAG.
This patch modifies SelectionDAGBuilder to construct SDNodes with associated
NoSignedWrap, NoUnsignedWrap and Exact flags coming from IR BinaryOperator
instructions.
Added a new SDNode type called 'BinaryWithFlagsSDNode' to allow accessing
nsw/nuw/exact flags during codegen.
Patch by Marcello Maggioni.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210467 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86')
-rw-r--r-- | test/CodeGen/X86/2014-05-30-CombineAddNSW.ll | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/test/CodeGen/X86/2014-05-30-CombineAddNSW.ll b/test/CodeGen/X86/2014-05-30-CombineAddNSW.ll new file mode 100644 index 0000000000..4580795880 --- /dev/null +++ b/test/CodeGen/X86/2014-05-30-CombineAddNSW.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; CHECK: addl + +; The two additions are the same , but have different flags. +; In theory this code should never be generated by the frontend, but this +; tries to test that two identical instructions with two different flags +; actually generate two different nodes. +; +; Normally the combiner would see this condition without the flags +; and optimize the result of the sub into a register clear +; (the final result would be 0). With the different flags though the combiner +; needs to keep the add + sub nodes, because the two nodes result as different +; nodes and so cannot assume that the subtraction of the two nodes +; generates 0 as result +define i32 @foo(i32 %a, i32 %b) { + %1 = add i32 %a, %b + %2 = add nsw i32 %a, %b + %3 = sub i32 %1, %2 + ret i32 %3 +} |