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| author | Weiming Zhao <weimingz@codeaurora.org> | 2013-12-06 17:56:48 +0000 |
|---|---|---|
| committer | Weiming Zhao <weimingz@codeaurora.org> | 2013-12-06 17:56:48 +0000 |
| commit | 1c6611db444c8e43d2b1dc9abe9ddf938e8bc09d (patch) | |
| tree | c24368e94bd53397afc0922e2a05f7dd08968b9f /test/DebugInfo | |
| parent | c008152a39a73188e0b21d25f225859d76e171ea (diff) | |
| download | llvm-1c6611db444c8e43d2b1dc9abe9ddf938e8bc09d.tar.gz llvm-1c6611db444c8e43d2b1dc9abe9ddf938e8bc09d.tar.bz2 llvm-1c6611db444c8e43d2b1dc9abe9ddf938e8bc09d.tar.xz | |
Bug 18149: [AArch32] VSel instructions has no ARMCC field
The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196588 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/DebugInfo')
0 files changed, 0 insertions, 0 deletions