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| author | Tim Northover <Tim.Northover@arm.com> | 2013-02-06 09:13:13 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-02-06 09:13:13 +0000 |
| commit | cbff068398a84ed488b7fdab5fea8e05500d385a (patch) | |
| tree | ec6a49b80b8b2f0aa75fd2eb4bc4a45bc6fc38fa /test/MC/AArch64 | |
| parent | 9e3b31345f0d17b757e183a8384db92616256926 (diff) | |
| download | llvm-cbff068398a84ed488b7fdab5fea8e05500d385a.tar.gz llvm-cbff068398a84ed488b7fdab5fea8e05500d385a.tar.bz2 llvm-cbff068398a84ed488b7fdab5fea8e05500d385a.tar.xz | |
Add AArch64 CRC32 instructions
These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/AArch64')
| -rw-r--r-- | test/MC/AArch64/basic-a64-instructions.s | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s index e3b1ea8326..ad3064e5e5 100644 --- a/test/MC/AArch64/basic-a64-instructions.s +++ b/test/MC/AArch64/basic-a64-instructions.s @@ -1435,6 +1435,23 @@ _func: // Data-processing (2 source) //------------------------------------------------------------------------------ + crc32b w5, w7, w20 + crc32h w28, wzr, w30 + crc32w w0, w1, w2 + crc32x w7, w9, x20 + crc32cb w9, w5, w4 + crc32ch w13, w17, w25 + crc32cw wzr, w3, w5 + crc32cx w18, w16, xzr +// CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a] +// CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a] +// CHECK: crc32w w0, w1, w2 // encoding: [0x20,0x48,0xc2,0x1a] +// CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a] +// CHECK: crc32cb w9, w5, w4 // encoding: [0xa9,0x50,0xc4,0x1a] +// CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a] +// CHECK: crc32cw wzr, w3, w5 // encoding: [0x7f,0x58,0xc5,0x1a] +// CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a] + udiv w0, w7, w10 udiv x9, x22, x4 sdiv w12, w21, w0 |