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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-01-10 04:38:31 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-01-10 04:38:31 +0000 |
| commit | 4eeee88e912cc03208b5ead91563a7519ec4ab73 (patch) | |
| tree | 25c464b871dfbdec9670639d8b4eed979568c4ab /test/MC/ARM/arm_addrmode2.s | |
| parent | d0a796e5dd03b23d48e085ed37dbe6579e1c58cd (diff) | |
| download | llvm-4eeee88e912cc03208b5ead91563a7519ec4ab73.tar.gz llvm-4eeee88e912cc03208b5ead91563a7519ec4ab73.tar.bz2 llvm-4eeee88e912cc03208b5ead91563a7519ec4ab73.tar.xz | |
ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
The ARM ARM indicates the mnemonics as follows:
ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.
Thanks to Joerg Sonnenberger for the tests!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198914 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM/arm_addrmode2.s')
| -rw-r--r-- | test/MC/ARM/arm_addrmode2.s | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/test/MC/ARM/arm_addrmode2.s b/test/MC/ARM/arm_addrmode2.s index ca99233b9b..a4fb9356db 100644 --- a/test/MC/ARM/arm_addrmode2.s +++ b/test/MC/ARM/arm_addrmode2.s @@ -4,27 +4,35 @@ @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6] @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6] @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4] +@ CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4] @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6] @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6] @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4] +@ CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4] @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6] @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6] @ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4] +@ CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4] @ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6] @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6] @ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4] +@ CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4] ldrt r1, [r0], r2 ldrt r1, [r0], r2, lsr #3 ldrt r1, [r0], #4 + ldrt r1, [r0] ldrbt r1, [r0], r2 ldrbt r1, [r0], r2, lsr #3 ldrbt r1, [r0], #4 + ldrbt r1, [r0] strt r1, [r0], r2 strt r1, [r0], r2, lsr #3 strt r1, [r0], #4 + strt r1, [r0] strbt r1, [r0], r2 strbt r1, [r0], r2, lsr #3 strbt r1, [r0], #4 + strbt r1, [r0] @ Pre-indexed @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7] |