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authorOwen Anderson <resistor@mac.com>2010-11-03 22:44:51 +0000
committerOwen Anderson <resistor@mac.com>2010-11-03 22:44:51 +0000
commitd966817f3cb87897cbec29c967b974924fe939ba (patch)
tree0db1ac722a81ce6eac28b7a5ac3adc6d71796e53 /test/MC/ARM/neon-bitwise-encoding.s
parent35b2de012d9404e3e9e4373e45f41711f752dd3a (diff)
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Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM/neon-bitwise-encoding.s')
-rw-r--r--test/MC/ARM/neon-bitwise-encoding.s5
1 files changed, 5 insertions, 0 deletions
diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s
index 13fe53cd14..345b6bb2d2 100644
--- a/test/MC/ARM/neon-bitwise-encoding.s
+++ b/test/MC/ARM/neon-bitwise-encoding.s
@@ -1,4 +1,5 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ XFAIL: *
@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2]
vand d16, d17, d16
@@ -14,6 +15,10 @@
vorr d16, d17, d16
@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2]
vorr q8, q8, q9
+@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2]
+ vorr.i32 d16, #0x1000000
+@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2]
+ vorr.i32 q8, #0x1000000
@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2]
vbic d16, d17, d16