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| author | Mihai Popa <mihail.popa@gmail.com> | 2013-06-11 09:39:51 +0000 |
|---|---|---|
| committer | Mihai Popa <mihail.popa@gmail.com> | 2013-06-11 09:39:51 +0000 |
| commit | 16ad92ad3cd0cbbaa4d0524d9f201dd5dbefa15a (patch) | |
| tree | 373783304fc9f7ec20d07f618e11fb22119bcb08 /test/MC/ARM | |
| parent | aa8003712e8b28bc4f263aeb79d8851146273a05 (diff) | |
| download | llvm-16ad92ad3cd0cbbaa4d0524d9f201dd5dbefa15a.tar.gz llvm-16ad92ad3cd0cbbaa4d0524d9f201dd5dbefa15a.tar.bz2 llvm-16ad92ad3cd0cbbaa4d0524d9f201dd5dbefa15a.tar.xz | |
This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM')
| -rw-r--r-- | test/MC/ARM/simple-fp-encoding.s | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index 0561b44907..d840e9cd79 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -157,6 +157,10 @@ vmrs r0, fpexc @ CHECK: vmrs r0, fpsid @ encoding: [0x10,0x0a,0xf0,0xee] vmrs r0, fpsid +@ CHECK: vmrs r1, fpinst @ encoding: [0x10,0x1a,0xf9,0xee] + vmrs r1, fpinst +@ CHECK: vmrs r8, fpinst2 @ encoding: [0x10,0x8a,0xfa,0xee] + vmrs r8, fpinst2 @ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee] vmsr fpscr, r0 @@ -164,6 +168,10 @@ vmsr fpexc, r0 @ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee] vmsr fpsid, r0 +@ CHECK: vmsr fpinst, r3 @ encoding: [0x10,0x3a,0xe9,0xee] + vmsr fpinst, r3 +@ CHECK: vmsr fpinst2, r4 @ encoding: [0x10,0x4a,0xea,0xee] + vmsr fpinst2, r4 vmov.f64 d16, #3.000000e+00 vmov.f32 s0, #3.000000e+00 |