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author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-04-27 04:29:32 +0000 |
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committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-04-27 04:29:32 +0000 |
commit | 86e4b7dadbc799967353ac5e85089697cd2c77e5 (patch) | |
tree | c538475dd70a3457933b2a5f0c2b523f5b4e2ed2 /test/MC/ARM | |
parent | 2d0d7fd085014eb4217545be06f57397808983d0 (diff) | |
download | llvm-86e4b7dadbc799967353ac5e85089697cd2c77e5.tar.gz llvm-86e4b7dadbc799967353ac5e85089697cd2c77e5.tar.bz2 llvm-86e4b7dadbc799967353ac5e85089697cd2c77e5.tar.xz |
COFF: move ARM COFF test to ARM directory
The COFF tests all assume X86. Just move the new COFF tests under ARM to
appease the build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM')
-rw-r--r-- | test/MC/ARM/coff-relocations.s | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/test/MC/ARM/coff-relocations.s b/test/MC/ARM/coff-relocations.s new file mode 100644 index 0000000000..6ebae709f6 --- /dev/null +++ b/test/MC/ARM/coff-relocations.s @@ -0,0 +1,101 @@ +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-RELOCATION + +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-ENCODING + + .syntax unified + .text + .thumb + + .global target + + .thumb_func +branch24t: + b target + +@ CHECK-ENCODING-LABEL: branch24t +@ CHECK-ENCODING-NEXT: b.w #0 + + .thumb_func +branch20t: + bcc target + +@ CHECK-ENCODING-LABEL: branch20t +@ CHECK-ENCODING-NEXT: blo.w #0 + + .thumb_func +blx23t: + bl target + +@ CHECK-ENCODING-LABEL: blx23t +@ CHECK-ENCODING-NEXT: bl #0 + + .thumb_func +mov32t: + movw r0, :lower16:target + movt r0, :upper16:target + blx r0 + +@ CHECK-ENCODING-LABEL: mov32t +@ CHECK-ENCODING-NEXT: movw r0, #0 +@ CHECK-ENCODING-NEXT: movt r0, #0 +@ CHECK-ENCODING-NEXT: blx r0 + + .thumb_func +addr32: + ldr r0, .Laddr32 + bx r0 + trap +.Laddr32: + .long target + +@ CHECK-ENCODING-LABEL: addr32 +@ CHECK-ENCODING-NEXT: ldr r0, [pc, #4] +@ CHECK-ENCODING-NEXT: bx r0 +@ CHECK-ENCODING-NEXT: trap +@ CHECK-ENCODING-NEXT: movs r0, r0 +@ CHECK-ENCODING-NEXT: movs r0, r0 + + .thumb_func +addr32nb: + ldr r0, .Laddr32nb + bx r0 + trap +.Laddr32nb: + .long target(imgrel) + +@ CHECK-ENCODING-LABEL: addr32nb +@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4] +@ CHECK-ENCODING-NEXT: bx r0 +@ CHECK-ENCODING-NEXT: trap +@ CHECK-ENCODING-NEXT: movs r0, r0 +@ CHECK-ENCODING-NEXT: movs r0, r0 + + .thumb_func +secrel: + ldr r0, .Lsecrel + bx r0 + trap +.Lsecrel: + .long target(secrel32) + +@ CHECK-ENCODING-LABEL: secrel +@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4] +@ CHECK-ENCODING-NEXT: bx r0 +@ CHECK-ENCODING-NEXT: trap +@ CHECK-ENCODING-NEXT: movs r0, r0 +@ CHECK-ENCODING-NEXT: movs r0, r0 + +@ CHECK-RELOCATION: Relocations [ +@ CHECK-RELOCATION: Section (1) .text { +@ CHCEK-RELOCATION: 0x0 IMAGE_REL_ARM_BRANCH24T +@ CHECK-RELOCATION: 0x4 IMAGE_REL_ARM_BRANCH20T +@ CHECK-RELOCATION: 0x8 IMAGE_REL_ARM_BLX23T +@ CHECK-RELOCATION: 0xC IMAGE_REL_ARM_MOV32T +@ CHECK-RELOCATION: 0x1C IMAGE_REL_ARM_ADDR32 +@ CHECK-RELOCATION: 0x28 IMAGE_REL_ARM_ADDR32NB +@ CHECK-RELOCATION: 0x34 IMAGE_REL_ARM_SECREL +@ CHECK-RELOCATION: } +@ CHECK-RELOCATION: ] + |