diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 00:16:18 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 00:16:18 +0000 |
| commit | 157536b1fb900e57efe042d48c7caeb87b1efd04 (patch) | |
| tree | b861e155cadcd26dcf931c9ed6daf6180e594d2f /test/MC/Disassembler | |
| parent | 597028cc2840d9182523bd0179a1f95ddd931dae (diff) | |
| download | llvm-157536b1fb900e57efe042d48c7caeb87b1efd04.tar.gz llvm-157536b1fb900e57efe042d48c7caeb87b1efd04.tar.bz2 llvm-157536b1fb900e57efe042d48c7caeb87b1efd04.tar.xz | |
Fix SRS/SRSW encoding bits.
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt | 11 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-SRS-arm.txt | 13 |
2 files changed, 24 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt new file mode 100644 index 0000000000..1fdfa8299c --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction +# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction +0x32 0xb1 0x99 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt new file mode 100644 index 0000000000..fdca9f9eae --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# Unknown format +# +# B6.1.10 SRS +# Inst{19-8} = 0xd05 +# Inst{7-5} = 0b000 +0x83 0x1c 0xc5 0xf8 |