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authorOwen Anderson <resistor@mac.com>2011-08-26 20:43:14 +0000
committerOwen Anderson <resistor@mac.com>2011-08-26 20:43:14 +0000
commit9ab0f25fc194b4315db1b87d38d4024054120bf6 (patch)
tree415f40669177f77045f724420e3833804b710e5d /test/MC/Disassembler
parentae5ea6cab040003f565775b132d243157b25a152 (diff)
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invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler')
-rw-r--r--test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
index e22f844413..e42e0de9b9 100644
--- a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
+++ b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding}
# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0