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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 13:18:59 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 13:18:59 +0000 |
| commit | 77ae274ae7fb3ca1fe26147a64efd323e59fbd8c (patch) | |
| tree | b4253c0bcd29b9562de9f4554f87b9a0d5d5b4bf /test/MC/Mips/mips64r6/valid.s | |
| parent | af0d72a6f9ef752ad871e53304d22fb5c930adb9 (diff) | |
| download | llvm-77ae274ae7fb3ca1fe26147a64efd323e59fbd8c.tar.gz llvm-77ae274ae7fb3ca1fe26147a64efd323e59fbd8c.tar.bz2 llvm-77ae274ae7fb3ca1fe26147a64efd323e59fbd8c.tar.xz | |
[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
Summary:
There is no change to the restrictions, just the result register is stored
once in the encoding rather than twice. The rt field is zero in
MIPS32r6/MIPS64r6.
Depends on D4119
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211019 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips/mips64r6/valid.s')
| -rw-r--r-- | test/MC/Mips/mips64r6/valid.s | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 99307f2b10..970ced2b24 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -154,3 +154,7 @@ lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7] + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52] |