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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-26 13:49:53 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-26 13:49:53 +0000 |
| commit | 8950dd127ad4cccd9dadf616b5057cf130f24ade (patch) | |
| tree | 8acf2ee447b8829ec3edf9a2c4cc013acf1a2895 /test/MC/PowerPC | |
| parent | 0b8594268feb1c804370541c7853e658caee0ae5 (diff) | |
| download | llvm-8950dd127ad4cccd9dadf616b5057cf130f24ade.tar.gz llvm-8950dd127ad4cccd9dadf616b5057cf130f24ade.tar.bz2 llvm-8950dd127ad4cccd9dadf616b5057cf130f24ade.tar.xz | |
[PowerPC] Accept 17-bit signed immediates for addis
The assembler currently strictly verifies that immediates for
s16imm operands are in range (-32768 ... 32767). This matches
the behaviour of the GNU assembler, with one exception: gas
allows, as a special case, operands in an extended range
(-65536 .. 65535) for the addis instruction only (and its
extended mnemonic lis).
The main reason for this seems to be to allow using unsigned
16-bit operands for lis, e.g. like lis %r1, 0xfedc.
Since this has been supported by gas for a long time, and
assembler source code seen "in the wild" actually exploits
this feature, this patch adds equivalent support to LLVM
for compatibility reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184946 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/PowerPC')
| -rw-r--r-- | test/MC/PowerPC/ppc64-errors.s | 8 | ||||
| -rw-r--r-- | test/MC/PowerPC/ppc64-operands.s | 8 |
2 files changed, 16 insertions, 0 deletions
diff --git a/test/MC/PowerPC/ppc64-errors.s b/test/MC/PowerPC/ppc64-errors.s index 1da5753046..8b6dd5395f 100644 --- a/test/MC/PowerPC/ppc64-errors.s +++ b/test/MC/PowerPC/ppc64-errors.s @@ -32,6 +32,14 @@ # CHECK-NEXT: ori 1, 2, 65536 ori 1, 2, 65536 +# Signed 16-bit immediate operands (extended range for addis) + +# CHECK: error: invalid operand for instruction + addis 1, 0, -65537 + +# CHECK: error: invalid operand for instruction + addis 1, 0, 65536 + # D-Form memory operands # CHECK: error: invalid register number diff --git a/test/MC/PowerPC/ppc64-operands.s b/test/MC/PowerPC/ppc64-operands.s index 5cc6a3c648..cb96fd4588 100644 --- a/test/MC/PowerPC/ppc64-operands.s +++ b/test/MC/PowerPC/ppc64-operands.s @@ -40,6 +40,14 @@ # CHECK: ori 1, 2, 65535 # encoding: [0x60,0x41,0xff,0xff] ori 1, 2, 65535 +# Signed 16-bit immediate operands (extended range for addis) + +# CHECK: addis 1, 0, 0 # encoding: [0x3c,0x20,0x00,0x00] + addis 1, 0, -65536 + +# CHECK: addis 1, 0, -1 # encoding: [0x3c,0x20,0xff,0xff] + addis 1, 0, 65535 + # D-Form memory operands # CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00] |