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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-24 11:55:21 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-24 11:55:21 +0000 |
| commit | e5a30f0ca22cc1ba97478e9fadcdef02d341004e (patch) | |
| tree | 1529ac5eb573f9db03f27be0e01f1df05f815c87 /test/MC/PowerPC | |
| parent | 9679c47a07386cbf3547a0927609c7ee080b2aab (diff) | |
| download | llvm-e5a30f0ca22cc1ba97478e9fadcdef02d341004e.tar.gz llvm-e5a30f0ca22cc1ba97478e9fadcdef02d341004e.tar.bz2 llvm-e5a30f0ca22cc1ba97478e9fadcdef02d341004e.tar.xz | |
[PowerPC] Support generic conditional branches in asm parser
This adds instruction patterns to cover the generic forms of
the conditional branch instructions. This allows the assembler
to support the generic mnemonics.
The compiler will still generate the various specific forms
of the instruction that were already supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184722 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/PowerPC')
| -rw-r--r-- | test/MC/PowerPC/ppc64-encoding.s | 38 |
1 files changed, 29 insertions, 9 deletions
diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s index cf6f7847d9..377000f1d2 100644 --- a/test/MC/PowerPC/ppc64-encoding.s +++ b/test/MC/PowerPC/ppc64-encoding.s @@ -18,15 +18,35 @@ # CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs bla target -# FIXME: bc 4, 10, target -# FIXME: bca 4, 10, target -# FIXME: bcl 4, 10, target -# FIXME: bcla 4, 10, target - -# FIXME: bclr 4, 10, 3 -# FIXME: bclrl 4, 10, 3 -# FIXME: bcctr 4, 10, 3 -# FIXME: bcctrl 4, 10, 3 +# CHECK: bc 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bc 4, 10, target +# CHECK: bca 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA10] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bca 4, 10, target +# CHECK: bcl 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA01] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bcl 4, 10, target +# CHECK: bcla 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA11] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bcla 4, 10, target + +# CHECK: bclr 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x20] + bclr 4, 10, 3 +# CHECK: bclr 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x20] + bclr 4, 10 +# CHECK: bclrl 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x21] + bclrl 4, 10, 3 +# CHECK: bclrl 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x21] + bclrl 4, 10 +# CHECK: bcctr 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x20] + bcctr 4, 10, 3 +# CHECK: bcctr 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x20] + bcctr 4, 10 +# CHECK: bcctrl 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x21] + bcctrl 4, 10, 3 +# CHECK: bcctrl 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x21] + bcctrl 4, 10 # Condition register instructions |