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| author | Ben Langmuir <ben.langmuir@intel.com> | 2013-09-12 15:51:31 +0000 |
|---|---|---|
| committer | Ben Langmuir <ben.langmuir@intel.com> | 2013-09-12 15:51:31 +0000 |
| commit | 1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f (patch) | |
| tree | 6a4093eec10f724f5f8bc99e58474ecfa2ec66e8 /test/MC/X86 | |
| parent | c0b12dfd0a83081c1ebbb55a89c7a2c1f98f1842 (diff) | |
| download | llvm-1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f.tar.gz llvm-1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f.tar.bz2 llvm-1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f.tar.xz | |
Partial support for Intel SHA Extensions (sha1rnds4)
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.
Support for the remaining instructions will follow in a separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/X86')
| -rw-r--r-- | test/MC/X86/x86_64-encoding.s | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/test/MC/X86/x86_64-encoding.s b/test/MC/X86/x86_64-encoding.s index cfdf87f3e3..54d8637529 100644 --- a/test/MC/X86/x86_64-encoding.s +++ b/test/MC/X86/x86_64-encoding.s @@ -120,6 +120,14 @@ movd %mm1, %edx // CHECK: fixup A - offset: 5, value: CPI1_0-4 pshufb CPI1_0(%rip), %xmm1 +// CHECK: sha1rnds4 $1, %xmm1, %xmm2 +// CHECK: encoding: [0x0f,0x3a,0xcc,0xd1,0x01] +sha1rnds4 $1, %xmm1, %xmm2 + +// CHECK: sha1rnds4 $1, (%rax), %xmm2 +// CHECK: encoding: [0x0f,0x3a,0xcc,0x10,0x01] +sha1rnds4 $1, (%rax), %xmm2 + // CHECK: movq 57005(,%riz), %rbx // CHECK: encoding: [0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00] movq 57005(,%riz), %rbx |