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| author | Kevin Enderby <enderby@apple.com> | 2012-05-17 22:18:01 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2012-05-17 22:18:01 +0000 |
| commit | 0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe (patch) | |
| tree | ff979e700e850c62069e8225e67072680143f90c /test/MC | |
| parent | bb8cef51dfe7bb59109786a0ca46ad165c39aa38 (diff) | |
| download | llvm-0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe.tar.gz llvm-0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe.tar.bz2 llvm-0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe.tar.xz | |
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/ARM/thumb2-mclass.s | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/test/MC/ARM/thumb2-mclass.s b/test/MC/ARM/thumb2-mclass.s index 10460f9145..df4e4c93b9 100644 --- a/test/MC/ARM/thumb2-mclass.s +++ b/test/MC/ARM/thumb2-mclass.s @@ -44,9 +44,21 @@ @------------------------------------------------------------------------------ msr apsr, r0 + msr apsr_nzcvq, r0 + msr apsr_g, r0 + msr apsr_nzcvqg, r0 msr iapsr, r0 + msr iapsr_nzcvq, r0 + msr iapsr_g, r0 + msr iapsr_nzcvqg, r0 msr eapsr, r0 + msr eapsr_nzcvq, r0 + msr eapsr_g, r0 + msr eapsr_nzcvqg, r0 msr xpsr, r0 + msr xpsr_nzcvq, r0 + msr xpsr_g, r0 + msr xpsr_nzcvqg, r0 msr ipsr, r0 msr epsr, r0 msr iepsr, r0 @@ -58,10 +70,22 @@ msr faultmask, r0 msr control, r0 -@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x80] -@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x80] -@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x80] -@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x80] +@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84] +@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c] +@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84] +@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c] +@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84] +@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c] +@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84] +@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c] @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80] @ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x80] @ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x80] |