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| author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:06 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:43:06 +0000 |
| commit | 3d41487f0efa0079bdf24b95d09bb3eb1590f6ed (patch) | |
| tree | 2c4c73fe567ab45ef40d3e412f604f6cd7ede8f2 /test/MC | |
| parent | 436fe613fc88c22f0e25d816f2c2e15c16b0c479 (diff) | |
| download | llvm-3d41487f0efa0079bdf24b95d09bb3eb1590f6ed.tar.gz llvm-3d41487f0efa0079bdf24b95d09bb3eb1590f6ed.tar.bz2 llvm-3d41487f0efa0079bdf24b95d09bb3eb1590f6ed.tar.xz | |
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/ARM64/spsel-sysreg.s | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/test/MC/ARM64/spsel-sysreg.s b/test/MC/ARM64/spsel-sysreg.s new file mode 100644 index 0000000000..e6ff4bf51a --- /dev/null +++ b/test/MC/ARM64/spsel-sysreg.s @@ -0,0 +1,24 @@ +// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +msr SPSel, #0 +msr SPSel, x0 +msr DAIFSet, #0 +msr ESR_EL1, x0 +mrs x0, SPSel +mrs x0, ESR_EL1 + +// CHECK: msr SPSEL, #0 // encoding: [0xbf,0x40,0x00,0xd5] +// CHECK: msr SPSEL, x0 // encoding: [0x00,0x42,0x18,0xd5] +// CHECK: msr DAIFSET, #0 // encoding: [0xdf,0x40,0x03,0xd5] +// CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5] +// CHECK: mrs x0, SPSEL // encoding: [0x00,0x42,0x38,0xd5] +// CHECK: mrs x0, ESR_EL1 // encoding: [0x00,0x52,0x38,0xd5] + + +msr DAIFSet, x0 +msr ESR_EL1, #0 +mrs x0, DAIFSet +// CHECK-ERRORS: error: invalid operand for instruction +// CHECK-ERRORS: error: invalid operand for instruction +// CHECK-ERRORS: error: invalid operand for instruction |