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authorBradley Smith <bradley.smith@arm.com>2014-04-09 14:44:36 +0000
committerBradley Smith <bradley.smith@arm.com>2014-04-09 14:44:36 +0000
commit42c672649ce57999db693d9f1c9995b8ffb684b4 (patch)
treea1fac52fa8cc40d017a3db607fc1b14cec45c2bb /test/MC
parent6a82fbc29ff24a77361b5f25fa19e9131926b8c2 (diff)
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[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
-rw-r--r--test/MC/Disassembler/ARM64/memory.txt10
1 files changed, 7 insertions, 3 deletions
diff --git a/test/MC/Disassembler/ARM64/memory.txt b/test/MC/Disassembler/ARM64/memory.txt
index 664f2b4db2..54556a10b8 100644
--- a/test/MC/Disassembler/ARM64/memory.txt
+++ b/test/MC/Disassembler/ARM64/memory.txt
@@ -83,6 +83,8 @@
0x64 0x00 0x00 0x39
0x85 0x50 0x00 0x39
0xe2 0x43 0x00 0x79
+ 0x00 0xe8 0x20 0x38
+ 0x00 0x48 0x20 0x38
# CHECK: str x4, [x3]
# CHECK: str x2, [sp, #32]
@@ -95,6 +97,8 @@
# CHECK: strb w4, [x3]
# CHECK: strb w5, [x4, #20]
# CHECK: strh w2, [sp, #32]
+# CHECK: strb w0, [x0, x0, sxtx]
+# CHECK: strb w0, [x0, w0, uxtw]
#-----------------------------------------------------------------------------
# Unscaled immediate loads and stores
@@ -422,11 +426,11 @@
0xe1 0x6b 0xa3 0x3c
0xe1 0x5b 0xa3 0x3c
-# CHECK: str h0, [x0, x0, uxtw]
+# CHECK: str h0, [x0, w0, uxtw]
# CHECK: str d1, [sp, x3]
-# CHECK: str d1, [sp, x3, uxtw #3]
+# CHECK: str d1, [sp, w3, uxtw #3]
# CHECK: str q1, [sp, x3]
-# CHECK: str q1, [sp, x3, uxtw #4]
+# CHECK: str q1, [sp, w3, uxtw #4]
#-----------------------------------------------------------------------------
# Load/Store exclusive