diff options
author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 10:00:45 +0000 |
---|---|---|
committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 10:00:45 +0000 |
commit | 5ee24f37af23feb0c74b0560fce6698148642305 (patch) | |
tree | e238f9419dc50e25f3e25ddb71d3b67e057bbd83 /test/MC | |
parent | 467e6ad2e5e971442727d073795587464b59f797 (diff) | |
download | llvm-5ee24f37af23feb0c74b0560fce6698148642305.tar.gz llvm-5ee24f37af23feb0c74b0560fce6698148642305.tar.bz2 llvm-5ee24f37af23feb0c74b0560fce6698148642305.tar.xz |
[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6
Summary:
The error message for the invalid.s cases isn't very helpful. It happens because
there is an instruction with a wider immediate that would have matched if the
NotMips32r6 predicate were true. I have some WIP to improve the message but it
affects most error messages for removed/re-encoded instructions on
MIPS32r6/MIPS64r6 and should therefore be a separate commit.
Depens on D4115
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211012 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
-rw-r--r-- | test/MC/Mips/mips1/valid.s | 4 | ||||
-rw-r--r-- | test/MC/Mips/mips2/valid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips3/valid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips32/valid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips32r2/valid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/valid.s | 4 | ||||
-rw-r--r-- | test/MC/Mips/mips4/valid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips5/valid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips64/valid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips64r2/valid.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips64r6/invalid.s | 6 | ||||
-rw-r--r-- | test/MC/Mips/mips64r6/valid.s | 4 |
13 files changed, 52 insertions, 38 deletions
diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s index d12b53b038..aacbfe5401 100644 --- a/test/MC/Mips/mips1/valid.s +++ b/test/MC/Mips/mips1/valid.s @@ -44,7 +44,7 @@ li $zero,-29889 lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwc3 $10,-32265($k0) lwl $s4,-4231($15) lwr $zero,-19147($gp) @@ -99,7 +99,7 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc3 $10,-32265($k0) swl $15,13694($s3) swr $s1,-26590($14) diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s index 4dd1149e42..a8ecb7d574 100644 --- a/test/MC/Mips/mips2/valid.s +++ b/test/MC/Mips/mips2/valid.s @@ -43,7 +43,7 @@ lb $24,-14515($10) lbu $8,30195($v1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldc3 $29,-28645($s1) lh $11,-8556($s5) lhu $s3,-22851($v0) @@ -52,7 +52,7 @@ ll $v0,-7321($s2) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwc3 $10,-32265($k0) lwl $s4,-4231($15) lwr $zero,-19147($gp) @@ -86,7 +86,7 @@ sb $s6,-19857($14) sc $15,18904($s3) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc3 $12,5835($10) sh $14,-6704($15) sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] @@ -115,7 +115,7 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc3 $10,-32265($k0) swl $15,13694($s3) swr $s1,-26590($14) diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s index f633e53637..548218a7fa 100644 --- a/test/MC/Mips/mips3/valid.s +++ b/test/MC/Mips/mips3/valid.s @@ -92,7 +92,7 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) lh $11,-8556($s5) @@ -103,7 +103,7 @@ lld $zero,-14736($ra) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -143,7 +143,7 @@ scd $15,-8243($sp) sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sh $14,-6704($15) @@ -173,7 +173,7 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) teqi $s5,-17504 diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s index d7bea03054..67fbca7a1f 100644 --- a/test/MC/Mips/mips32/valid.s +++ b/test/MC/Mips/mips32/valid.s @@ -50,7 +50,7 @@ lb $24,-14515($10) lbu $8,30195($v1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] lh $11,-8556($s5) lhu $s3,-22851($v0) li $at,-29773 @@ -58,7 +58,7 @@ ll $v0,-7321($s2) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) madd $s6,$13 @@ -113,7 +113,7 @@ sb $s6,-19857($14) sc $15,18904($s3) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sh $14,-6704($15) sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] @@ -141,7 +141,7 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) teqi $s5,-17504 diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index ba5030a52a..4d13bba52b 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -57,7 +57,7 @@ lb $24,-14515($10) lbu $8,30195($v1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldxc1 $f8,$s7($15) lh $11,-8556($s5) lhu $s3,-22851($v0) @@ -67,7 +67,7 @@ luxc1 $f19,$s6($s5) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwxc1 $f12,$s1($s8) @@ -138,7 +138,7 @@ sb $s6,-19857($14) sc $15,18904($s3) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdxc1 $f11,$10($14) seb $25,$15 seh $v1,$12 @@ -170,7 +170,7 @@ suxc1 $f12,$k1($13) sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) diff --git a/test/MC/Mips/mips32r6/invalid.s b/test/MC/Mips/mips32r6/invalid.s index 8202dbe595..82cb5ab494 100644 --- a/test/MC/Mips/mips32r6/invalid.s +++ b/test/MC/Mips/mips32r6/invalid.s @@ -1,10 +1,14 @@ -# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. -# invalid set of operands or operand's restrictions not met). +# Instructions that are available for the current ISA but should be rejected by +# the assembler (e.g. invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1 # RUN: FileCheck %s < %t1 -check-prefix=ASM .text .set noreorder + .set noat jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 7877f664e4..3364ed9003 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -132,3 +132,7 @@ jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] + ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] + sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] + swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s index 4b328814e1..0f6bbf0875 100644 --- a/test/MC/Mips/mips4/valid.s +++ b/test/MC/Mips/mips4/valid.s @@ -94,7 +94,7 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) ldxc1 $f8,$s7($15) @@ -106,7 +106,7 @@ lld $zero,-14736($ra) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -160,7 +160,7 @@ scd $15,-8243($sp) sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) @@ -191,7 +191,7 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s index 8730ab6fca..69a5e9eb6b 100644 --- a/test/MC/Mips/mips5/valid.s +++ b/test/MC/Mips/mips5/valid.s @@ -94,7 +94,7 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) ldxc1 $f8,$s7($15) @@ -107,7 +107,7 @@ luxc1 $f19,$s6($s5) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -161,7 +161,7 @@ scd $15,-8243($sp) sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) @@ -193,7 +193,7 @@ suxc1 $f12,$k1($13) sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index 6841c3df8d..3b4f468122 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -99,7 +99,7 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) ldxc1 $f8,$s7($15) @@ -112,7 +112,7 @@ luxc1 $f19,$s6($s5) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -175,7 +175,7 @@ scd $15,-8243($sp) sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) @@ -207,7 +207,7 @@ suxc1 $f12,$k1($13) sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index c74c8e36a2..f812c53187 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -113,7 +113,7 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) ldxc1 $f8,$s7($15) @@ -126,7 +126,7 @@ luxc1 $f19,$s6($s5) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -200,7 +200,7 @@ scd $15,-8243($sp) sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) @@ -234,7 +234,7 @@ suxc1 $f12,$k1($13) sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s index 4b80d6d5c2..1b01827368 100644 --- a/test/MC/Mips/mips64r6/invalid.s +++ b/test/MC/Mips/mips64r6/invalid.s @@ -1,10 +1,12 @@ -# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. -# invalid set of operands or operand's restrictions not met). +# Instructions that are available for the current ISA but should be rejected by +# the assembler (e.g. invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1 # RUN: FileCheck %s < %t1 -check-prefix=ASM .text .set noreorder + .set noat jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 8a2030649d..b8274829b0 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -146,3 +146,7 @@ jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] + ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] + sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] + swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] |