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| author | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-08 13:43:59 +0000 |
|---|---|---|
| committer | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-08 13:43:59 +0000 |
| commit | ae50ddb2aeaec7dd91ef8db3918688c104a6baed (patch) | |
| tree | f621d6c72507ef0fe41347a12f3cbc66b486824c /test/MC | |
| parent | 46e136c952e0242308db2682ba2ec4020cdcd006 (diff) | |
| download | llvm-ae50ddb2aeaec7dd91ef8db3918688c104a6baed.tar.gz llvm-ae50ddb2aeaec7dd91ef8db3918688c104a6baed.tar.bz2 llvm-ae50ddb2aeaec7dd91ef8db3918688c104a6baed.tar.xz | |
ARM: enforce SRS decoding constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-SRS-arm.txt | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt index eedd05cea6..bf9aac46c9 100644 --- a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt @@ -1,5 +1,3 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- @@ -10,4 +8,10 @@ # B6.1.10 SRS # Inst{19-8} = 0xd05 # Inst{7-5} = 0b000 -0x83 0x1c 0xc5 0xf8 +# RUN: echo "0x83 0x1c 0xc5 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s + +# RUN: echo "0x00 0x00 0x20 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0xff 0xff 0xaf 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x13 0x00 0xa0 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding |