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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-12 10:54:16 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-12 10:54:16 +0000 |
| commit | d94bc707c46c29c1dce9dd276b603ccff3ebfa83 (patch) | |
| tree | ade5d9e6265e35d35e49fa9b352823484b37de48 /test/MC | |
| parent | bf4e625cf107715a3643cae35e83e012db0670b5 (diff) | |
| download | llvm-d94bc707c46c29c1dce9dd276b603ccff3ebfa83.tar.gz llvm-d94bc707c46c29c1dce9dd276b603ccff3ebfa83.tar.bz2 llvm-d94bc707c46c29c1dce9dd276b603ccff3ebfa83.tar.xz | |
[mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6
Summary:
This patch disables madd/maddu/msub/msubu in both the assembler and code
generator.
Depends on D3896
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210762 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips32.s | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/test/MC/Mips/mips32r6/invalid-mips32.s b/test/MC/Mips/mips32r6/invalid-mips32.s new file mode 100644 index 0000000000..bce10cb5ea --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips32.s @@ -0,0 +1,13 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled |